Guest User

Untitled

a guest
Feb 23rd, 2020
114
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1.  
  2. // full_machine: execute a series of MIPS instructions from an instruction cache
  3. //
  4. // except (output) - set to 1 when an unrecognized instruction is to be executed.
  5. // clock (input) - the clock signal
  6. // reset (input) - set to 1 to set all registers to zero, set to 0 for normal execution.
  7.  
  8. module full_machine(except, clock, reset);
  9. output except;
  10. input clock, reset;
  11.  
  12. wire [31:0] inst;
  13. wire [31:0] PC;
  14.  
  15. wire [31:0] nextPC, PCplusfour, branchOut, branchOffset, rsData, jump, imm, luiConnect, memReadout, rdData, B, rtData, out, sltout, dataOut, byte_load_connect, byteout, new_negative, Bout, rdDatafinal, addmData;
  16. wire [4:0] Rdest;
  17. wire [2:0] alu_op;
  18. wire [1:0] control_type, alu_src2;
  19. wire rd_src, wr_enable, word_we, byte_we, byte_load, lui, slt, zero, mem_read, overflow, negative, addm;
  20.  
  21.  
  22. assign jump[31:28] = PC[31:28];
  23. assign jump[27:2] = inst[25:0];
  24. assign jump[1:0] = 0;
  25. assign luiConnect[31:16] = inst[15:0];
  26. assign luiConnect[15:0] = 0;
  27. assign byte_load_connect[31:8] = 0;
  28. assign new_negative[0] = negative;
  29. assign new_negative[31:1] = 0;
  30.  
  31.  
  32. //Register, Instruction, Decoder Initializations
  33. register #(32) PC_reg(PC[31:0], nextPC[31:0], clock, 1'b1, reset);
  34. instruction_memory im(inst[31:0], PC[31:2]);
  35. mips_decode m1(alu_op[2:0], wr_enable, rd_src, alu_src2[1:0], except, control_type[1:0], mem_read, word_we, byte_we, byte_load, slt, lui, addm, inst[31:26], inst[5:0], zero);
  36. data_mem dm1(dataOut[31:0], out[31:0], rtData[31:0], word_we, byte_we, clock, reset);
  37. regfile rf (rsData[31:0], rtData[31:0], inst[25:21], inst[20:16], Rdest[4:0], rdData[31:0], wr_enable, clock, reset);
  38.  
  39.  
  40. //ALU Creation
  41. alu32 a1(PCplusfour[31:0], , , , PC[31:0], 32'h4, `ALU_ADD);
  42. alu32 a2(branchOut[31:0], , , , PCplusfour[31:0], branchOffset[31:0], `ALU_ADD);
  43. alu32 a3(out[31:0], overflow, zero, negative, rsData[31:0], B[31:0], alu_op[2:0]);
  44. alu32 a4(addmData[31:0], , , , rtData[31:0], dataOut[31:0], 3'b010);
  45.  
  46.  
  47. //Mux2v Module Creations
  48. mux2v m1(B[31:0], Bout[31:0], 32'b0, addm);
  49. mux2v m2(rdData[31:0], rdDatafinal[31:0], addmData[31:0], addm);
  50. mux2v #(5) m3(Rdest[4:0], inst[15:11], inst[20:16], rd_src);
  51. mux2v #(32) m4(rdDatafinal[31:0], memReadout[31:0], luiConnect[31:0], lui);
  52. mux2v #(32) m5(sltout[31:0], out[31:0], new_negative, slt);
  53. mux2v #(32) m6(memReadout[31:0], sltout[31:0], byteout[31:0], mem_read);
  54. mux2v #(32) m7(byteout[31:0], dataOut[31:0], byte_load_connect[31:0], byte_load);
  55. mux2v #(32) m8(Bout[31:0], rtData[31:0], imm[31:0], alu_src2);
  56.  
  57.  
  58.  
  59. mux4v mcontrol(nextPC[31:0], PCplusfour[31:0], branchOut[31:0], jump, rsData, control_type);
  60. mux4v #(8) mdataout(byte_load_connect[7:0], dataOut[7:0], dataOut[15:8], dataOut[23:16], dataOut[31:24], out[1:0]);
  61.  
  62.  
  63.  
  64. shift_left_two sl1(branchOffset, imm[29:0]);
  65. sign_extender s1(imm, inst[15:0]);
  66. /* add other modules */
  67.  
  68. endmodule // full_machine
  69.  
  70. module sign_extender (imm, inst);
  71. output [31:0] imm;
  72. input [15:0] inst;
  73. assign imm = {{16{inst[15]}}, inst[15:0]};
  74.  
  75. endmodule // sign_extender
  76.  
  77. module shift_left_two (branchOffset, imm);
  78. output [31:0] branchOffset;
  79. input [29:0] imm;
  80. assign branchOffset[31:2] = imm[29:0];
  81. assign branchOffset[1:0] = 0;
  82.  
  83. endmodule // shift_left_two
RAW Paste Data