diff --git a/fpga/ram_reader.v b/fpga/ram_reader.v
index 4c57404..4a7a3cf 100644
--- a/fpga/ram_reader.v
+++ b/fpga/ram_reader.v
@@ -13,6 +13,7 @@ module ram_reader (
 	p_rd_clk,
 	p_rd_en,
 	p_rd_data,
+	p_rd_empty,

 	// contents of the address
 	data_out
@@ -32,6 +33,7 @@ module ram_reader (
 	output p_rd_clk;
 	output reg p_rd_en;
 	input [31:0] p_rd_data;
+	input p_rd_empty;

 	// contents of the address
 	output reg [31:0] data_out;
@@ -107,8 +109,11 @@ module ram_reader (
 					// bring en low again
 					p_cmd_en <= 1'b0;

-					// now we're done
-					cur_state <= S_READ_ENABLE;
+					// wait for data
+					if(p_rd_empty)
+						cur_state <= S_SEND_CMD_DONE;
+					else
+						cur_state <= S_READ_ENABLE;
 				end

 				// bring up the write enable line
diff --git a/fpga/top.v b/fpga/top.v
index 84bd8ea..fed98eb 100644
--- a/fpga/top.v
+++ b/fpga/top.v
@@ -313,6 +313,7 @@ module top  #
 		.p_rd_clk(p3_rd_clk),
 		.p_rd_en(c3_p3_rd_en),
 		.p_rd_data(c3_p3_rd_data),
+		.p_rd_empty(c3_p3_rd_empty),

 		// output of the whatever memory address was read
 		.data_out(data_out)