-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

-- Declaration de l'entité. Module de test aucune E/S
 entity TestModule2 is
 -- Port ( );
 end TestModule2;

 architecture Behavioral of TestModule2 is
 --declaration des variables utilisées et des sous-modules
 component Module2
Port ( a : in STD_LOGIC;
 b : in STD_LOGIC;
 c : in STD_LOGIC;
 d : out STD_LOGIC;
 e : out STD_LOGIC
);
 end component;

  signal A : STD_LOGIC :='0';
  signal B : STD_LOGIC :='0';
  signal C : STD_LOGIC :='0';
  signal D : STD_LOGIC;
  signal E : STD_LOGIC;
 -- declaration d'une constante de temps
 constant period:time :=10 ns;

 begin
 -- process de generation de toute les cas possible de l'entrée.
 genereSel: process
 begin
 a <='0';
 b <='0';
 c <='0';
 wait for period;
 a <='0';
 b <='0';
 c <='1';
 wait for period;
 a <='0';
 b <='1';
 c <='0';
 wait for period;
 a <='0';
 b <='1';
 c <='1';
 wait for period;
 a <='1';
 b <='0';
 c <='0';
 wait for period;
 a <='1';
 b <='0';
 c <='1';
 wait for period;
 a <='1';
 b <='1';
 c <='0';
 wait for period;
 a <='1';
 b <='1';
 c <='1';
 wait; -- will wait for ever
 end process;

 -- process Module1
 Affiche : Module2 PORT MAP(
a,b,c,d,e
 );
 end Behavioral;