library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;

entity lab92 is
Port ( clk  : in STD_LOGIC;
    srst : in STD_LOGIC;
    x1   : in STD_LOGIC_VECTOR (2 downto 0);
    x2   : in STD_LOGIC_VECTOR (2 downto 0);
    btn  : in STD_LOGIC;
    y    : out STD_LOGIC_VECTOR (7 downto 0));
end lab92;

architecture Behavioral of lab92 is
TYPE STATE_TYPE IS (s0,s1,s2,s3);--Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;--Declare any pre-registered internal signals
SIGNAL y_cld : std_logic_vector(7 downto 0);
signal sum   : std_logic_vector (7 downto 0) := (others => '0');
signal mult  : std_logic_vector (7 downto 0) := (others => '0');
signal x11 : std_logic_vector (4 downto 0) := (others => '0');
signal gcntr : std_logic_vector (7 downto 0);
signal cntr : std_logic_vector (25 downto 0) := (others => '0');
signal cntr25d : std_logic;
signal en : std_logic;
signal d_y : std_logic_vector (7 downto 0);
component lab72 is
Port ( clk : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR(7 downto 0));
end component lab72;
component gc is
Port (  clk : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR (7 downto 0));
end component gc;
begin
process(clk) begin
    if rising_edge(clk) then
        cntr <= unsigned(cntr) +1;
    end if;
end process;
process(clk) begin
    if rising_edge(clk) then
        cntr25d <= cntr(25);
    end if;
end process;
en <= cntr(25) and (not cntr25d);
clocked_proc : process(clk) begin
    if rising_edge(clk) then
        if srst = '1' then
            current_state <= s0;
        else
            current_state <= next_state;
        end if;
    end if;
end process;
nextstate_proc : process(btn, current_state) begin
    case current_state is
        when s0 =>
            if btn = '1' and en = '1' then
                next_state <= s1;
            end if;
        when s1 =>
            if btn = '1' and en = '1' then
                next_state <= s2;
            end if;
        when s2 =>
            if btn = '1' and en = '1' then
                next_state <= s3;
            end if;
        when s3 =>
            if btn = '1' and en = '1' then
                next_state <= s0;
            end if;
        when others =>
            next_state <= s0;
    end case;
end process;
waiting : lab72
    port map( clk => clk,
        dout => y_cld);
gccntr : gc
    port map( clk => clk,
        dout => gcntr);
output_proc : process(current_state) begin
    if current_state = s1 then
        x11(2 downto 0) <= x1;
        sum <= sxt(unsigned(x11) + unsigned(x2),8);
    elsif current_state = s2 then
        x11(2 downto 0) <= x1;
        mult <= sxt(unsigned(x11) * unsigned(x2),8);
    end if;
end process;
out_proc : process(clk) begin
    if rising_edge(clk) then
        if current_state = s0 then
            d_y <= y_cld;
        elsif current_state = s1 then
            d_y <= sum;
        elsif current_state = s2 then
            d_y <= mult;
        else
            d_y <= gcntr;
        end if;
    end if;
end process;
y <= d_y;
end architecture;