DigitalClock_LAB_try2

`timescale 1ns / 1ps

module dc_clk(input clk, input reset, output out_clk);

    reg [20:0] ctr;   //change it back to 23
    assign out_clk = ctr[20];

    always@(posedge clk) begin
        ctr = (reset == 1)?(0):(ctr + 1);
    end

endmodule

module en_clk(input clk, input reset, output out_clk);

    reg [15:0] ctr;
    assign out_clk = ctr[15];

    always@(posedge clk) begin
        ctr = (reset == 1)?(0):(ctr + 1);
    end

endmodule


module digital_clock(input clk, input reset1, input reset2, output reg [3:0] EN, output reg [6:0] y, output reg colon
    );

    reg [5:0] s;
    reg [5:0] m;
    reg [5:0] h;

    reg [1:0] en_ctr;

    wire out_clk1, out_clk2;

    dc_clk dc1(clk, reset1,out_clk1);
    en_clk en1(clk, reset2, out_clk2);

    always@(posedge out_clk1) begin

        if (reset1 == 1) begin
            s = 0;
            m = 0;
            h = 0;
        end

        else begin
            colon = ~colon;
            if (s == 60) s = 0;
            else s = s + 1;


            if (s == 60) begin
                m = m + 1;
            end

            if (m == 60) begin
                h = h + 1;
            end

        end

    end



    always@(posedge out_clk2) begin

    if (reset2 == 1) begin
        EN = 4'b1110;
        en_ctr = 0;
    end

    else begin

        if (en_ctr == 0) begin
            EN = 4'b1110;
            case(m%10)
            0:y = 7'b0000001;
            1:y = 7'b1001111;
            2:y = 7'b0010010;
            3:y = 7'b0000110;
            4:y = 7'b1001100;
            5:y = 7'b0100100;
            6:y = 7'b0100000;
            7:y = 7'b0001111;
            8:y = 7'b0000000;
            9:y = 7'b0000100;

            endcase
        end

        else if (en_ctr == 1) begin
            EN = 4'b1101;
            case(m/10)
            0:y = 7'b0000001;
            1:y = 7'b1001111;
            2:y = 7'b0010010;
            3:y = 7'b0000110;
            4:y = 7'b1001100;
            5:y = 7'b0100100;
            6:y = 7'b0100000;
            7:y = 7'b0001111;
            8:y = 7'b0000000;
            9:y = 7'b0000100;

            endcase
        end

        else if (en_ctr == 2) begin
            EN = 4'b1011;
            case(h%10)
            0:y = 7'b0000001;
            1:y = 7'b1001111;
            2:y = 7'b0010010;
            3:y = 7'b0000110;
            4:y = 7'b1001100;
            5:y = 7'b0100100;
            6:y = 7'b0100000;
            7:y = 7'b0001111;
            8:y = 7'b0000000;
            9:y = 7'b0000100;

            endcase
        end

        else if (en_ctr == 3) begin
            EN = 4'b0111;
            case(h/10)
            0:y = 7'b0000001;
            1:y = 7'b1001111;
            2:y = 7'b0010010;
            3:y = 7'b0000110;
            4:y = 7'b1001100;
            5:y = 7'b0100100;
            6:y = 7'b0100000;
            7:y = 7'b0001111;
            8:y = 7'b0000000;
            9:y = 7'b0000100;

            endcase
        end

        en_ctr = en_ctr + 1;


    end


    end

endmodule