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Oct 18th, 2021
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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x1>;
  5. #size-cells = <0x1>;
  6. compatible = "noname,board", "ralink,mt7620a-soc";
  7. model = "BatteryPoE";
  8.  
  9.  
  10. cpus {
  11. #address-cells = <0x1>;
  12. #size-cells = <0x0>;
  13.  
  14. cpu@0 {
  15. compatible = "mips,mips24KEc";
  16. reg = <0x0>;
  17. };
  18. };
  19.  
  20. chosen {
  21. bootargs = "console=ttyS0,115200";
  22. };
  23.  
  24. cpuintc {
  25. #address-cells = <0x0>;
  26. #interrupt-cells = <0x1>;
  27. interrupt-controller;
  28. compatible = "mti,cpu-interrupt-controller";
  29. linux,phandle = <0x3>;
  30. phandle = <0x3>;
  31. };
  32.  
  33. aliases {
  34. spi0 = "/palmbus@10000000/spi@b00";
  35. spi1 = "/palmbus@10000000/spi@b40";
  36. serial0 = "/palmbus@10000000/uartlite@c00";
  37. led-boot = "/leds/power";
  38. led-failsafe = "/leds/power";
  39. led-running = "/leds/power";
  40. led-upgrade = "/leds/power";
  41. };
  42.  
  43. palmbus@10000000 {
  44. compatible = "palmbus";
  45. reg = <0x10000000 0x200000>;
  46. ranges = <0x0 0x10000000 0x1fffff>;
  47. #address-cells = <0x1>;
  48. #size-cells = <0x1>;
  49.  
  50. sysc@0 {
  51. compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc", "syscon";
  52. reg = <0x0 0x100>;
  53. linux,phandle = <0xa>;
  54. phandle = <0xa>;
  55. };
  56.  
  57. timer@100 {
  58. compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
  59. reg = <0x100 0x20>;
  60. interrupt-parent = <0x1>;
  61. interrupts = <0x1>;
  62. };
  63.  
  64. watchdog@120 {
  65. compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
  66. reg = <0x120 0x10>;
  67. resets = <0x2 0x8>;
  68. reset-names = "wdt";
  69. interrupt-parent = <0x1>;
  70. interrupts = <0x1>;
  71. };
  72.  
  73. intc@200 {
  74. compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
  75. reg = <0x200 0x100>;
  76. resets = <0x2 0x13>;
  77. reset-names = "intc";
  78. interrupt-controller;
  79. #interrupt-cells = <0x1>;
  80. interrupt-parent = <0x3>;
  81. interrupts = <0x2>;
  82. linux,phandle = <0x1>;
  83. phandle = <0x1>;
  84. };
  85.  
  86. memc@300 {
  87. compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
  88. reg = <0x300 0x100>;
  89. resets = <0x2 0x14>;
  90. reset-names = "mc";
  91. interrupt-parent = <0x1>;
  92. interrupts = <0x3>;
  93. };
  94.  
  95. uart@500 {
  96. compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  97. reg = <0x500 0x100>;
  98. resets = <0x2 0xc>;
  99. reset-names = "uart";
  100. interrupt-parent = <0x1>;
  101. interrupts = <0x5>;
  102. reg-shift = <0x2>;
  103. status = "disabled";
  104. };
  105.  
  106. gpio@600 {
  107. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  108. reg = <0x600 0x34>;
  109. resets = <0x2 0xd>;
  110. reset-names = "pio";
  111. interrupt-parent = <0x1>;
  112. interrupts = <0x6>;
  113. gpio-controller;
  114. #gpio-cells = <0x2>;
  115. ralink,gpio-base = <0x0>;
  116. ralink,nr-gpio = <0x18>;
  117. ralink,register-map = [00 04 08 0c 20 24 28 2c 30 34];
  118. linux,phandle = <0x11>;
  119. phandle = <0x11>;
  120. };
  121.  
  122. gpio@638 {
  123. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  124. reg = <0x638 0x24>;
  125. interrupt-parent = <0x1>;
  126. interrupts = <0x6>;
  127. gpio-controller;
  128. #gpio-cells = <0x2>;
  129. ralink,gpio-base = <0x18>;
  130. ralink,nr-gpio = <0x10>;
  131. ralink,register-map = [00 04 08 0c 10 14 18 1c 20 24];
  132. status = "disabled";
  133. };
  134.  
  135. gpio@660 {
  136. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  137. reg = <0x660 0x24>;
  138. interrupt-parent = <0x1>;
  139. interrupts = <0x6>;
  140. gpio-controller;
  141. #gpio-cells = <0x2>;
  142. ralink,gpio-base = <0x28>;
  143. ralink,nr-gpio = <0x20>;
  144. ralink,register-map = [00 04 08 0c 10 14 18 1c 20 24];
  145. status = "disabled";
  146. };
  147.  
  148. gpio@688 {
  149. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  150. reg = <0x688 0x24>;
  151. interrupt-parent = <0x1>;
  152. interrupts = <0x6>;
  153. gpio-controller;
  154. #gpio-cells = <0x2>;
  155. ralink,gpio-base = <0x48>;
  156. ralink,nr-gpio = <0x1>;
  157. ralink,register-map = [00 04 08 0c 10 14 18 1c 20 24];
  158. status = "okay";
  159. linux,phandle = <0x14>;
  160. phandle = <0x14>;
  161. };
  162.  
  163. i2c@900 {
  164. compatible = "ralink,rt2880-i2c";
  165. reg = <0x900 0x100>;
  166. resets = <0x2 0x10>;
  167. reset-names = "i2c";
  168. #address-cells = <0x1>;
  169. #size-cells = <0x0>;
  170. status = "disabled";
  171. pinctrl-names = "default";
  172. pinctrl-0 = <0x4>;
  173. };
  174.  
  175. i2s@a00 {
  176. compatible = "mediatek,mt7620-i2s";
  177. reg = <0xa00 0x100>;
  178. resets = <0x2 0x11>;
  179. reset-names = "i2s";
  180. interrupt-parent = <0x1>;
  181. interrupts = <0xa>;
  182. txdma-req = <0x2>;
  183. rxdma-req = <0x3>;
  184. dmas = <0x5 0x4 0x5 0x6>;
  185. dma-names = "tx", "rx";
  186. status = "disabled";
  187. };
  188.  
  189. spi@b00 {
  190. compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
  191. reg = <0xb00 0x40>;
  192. resets = <0x2 0x12>;
  193. reset-names = "spi";
  194. #address-cells = <0x1>;
  195. #size-cells = <0x0>;
  196. status = "okay";
  197. pinctrl-names = "default";
  198. pinctrl-0 = <0x6>;
  199.  
  200. m25p80@0 {
  201. compatible = "jedec,spi-nor";
  202. reg = <0x0>;
  203. spi-max-frequency = <0x2dc6c00>;
  204.  
  205. partitions {
  206. compatible = "fixed-partitions";
  207. #address-cells = <0x1>;
  208. #size-cells = <0x1>;
  209.  
  210. partition@0 {
  211. label = "u-boot";
  212. reg = <0x0 0x30000>;
  213. read-only;
  214. };
  215.  
  216. partition@30000 {
  217. label = "u-boot-env";
  218. reg = <0x30000 0x10000>;
  219. read-only;
  220. };
  221.  
  222. partition@40000 {
  223. label = "factory";
  224. reg = <0x40000 0x10000>;
  225. linux,phandle = <0xd>;
  226. phandle = <0xd>;
  227. };
  228.  
  229. partition@50000 {
  230. compatible = "denx,uimage";
  231. label = "firmware";
  232. reg = <0x50000 0xfb0000>;
  233. };
  234. };
  235. };
  236. };
  237.  
  238. spi@b40 {
  239. compatible = "ralink,rt2880-spi";
  240. reg = <0xb40 0x60>;
  241. resets = <0x2 0x12>;
  242. reset-names = "spi";
  243. #address-cells = <0x1>;
  244. #size-cells = <0x0>;
  245. status = "disabled";
  246. pinctrl-names = "default";
  247. pinctrl-0 = <0x7>;
  248. };
  249.  
  250. uartlite@c00 {
  251. compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  252. reg = <0xc00 0x100>;
  253. resets = <0x2 0x13>;
  254. reset-names = "uartl";
  255. interrupt-parent = <0x1>;
  256. interrupts = <0xc>;
  257. reg-shift = <0x2>;
  258. pinctrl-names = "default";
  259. pinctrl-0 = <0x8>;
  260. };
  261.  
  262. systick@d00 {
  263. compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
  264. reg = <0xd00 0x10>;
  265. resets = <0x2 0x1c>;
  266. reset-names = "intc";
  267. interrupt-parent = <0x3>;
  268. interrupts = <0x7>;
  269. };
  270.  
  271. pcm@2000 {
  272. compatible = "ralink,mt7620a-pcm";
  273. reg = <0x2000 0x800>;
  274. resets = <0x2 0xb>;
  275. reset-names = "pcm";
  276. interrupt-parent = <0x1>;
  277. interrupts = <0x4>;
  278. status = "disabled";
  279. };
  280.  
  281. gdma@2800 {
  282. compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma";
  283. reg = <0x2800 0x800>;
  284. resets = <0x2 0xe>;
  285. reset-names = "dma";
  286. interrupt-parent = <0x1>;
  287. interrupts = <0x7>;
  288. #dma-cells = <0x1>;
  289. #dma-channels = <0x10>;
  290. #dma-requests = <0x10>;
  291. status = "disabled";
  292. linux,phandle = <0x5>;
  293. phandle = <0x5>;
  294. };
  295. };
  296.  
  297. pinctrl {
  298. compatible = "ralink,rt2880-pinmux";
  299. pinctrl-names = "default";
  300. pinctrl-0 = <0x9>;
  301.  
  302. pinctrl0 {
  303. linux,phandle = <0x9>;
  304. phandle = <0x9>;
  305.  
  306. gpio {
  307. ralink,group = "i2c", "wled", "uartf";
  308. ralink,function = "gpio";
  309. };
  310. };
  311.  
  312. pcm_i2s {
  313.  
  314. pcm_i2s {
  315. ralink,group = "uartf";
  316. ralink,function = "pcm i2s";
  317. };
  318. };
  319.  
  320. uartf_gpio {
  321.  
  322. uartf_gpio {
  323. ralink,group = "uartf";
  324. ralink,function = "gpio uartf";
  325. };
  326. };
  327.  
  328. gpio_i2s {
  329.  
  330. gpio_i2s {
  331. ralink,group = "uartf";
  332. ralink,function = "gpio i2s";
  333. };
  334. };
  335.  
  336. spi_pins {
  337. linux,phandle = <0x6>;
  338. phandle = <0x6>;
  339.  
  340. spi_pins {
  341. ralink,group = "spi";
  342. ralink,function = "spi";
  343. };
  344. };
  345.  
  346. spi1 {
  347. linux,phandle = <0x7>;
  348. phandle = <0x7>;
  349.  
  350. spi1 {
  351. ralink,group = "spi refclk";
  352. ralink,function = "spi refclk";
  353. };
  354. };
  355.  
  356. i2c_pins {
  357. linux,phandle = <0x4>;
  358. phandle = <0x4>;
  359.  
  360. i2c_pins {
  361. ralink,group = "i2c";
  362. ralink,function = "i2c";
  363. };
  364. };
  365.  
  366. uartlite {
  367. linux,phandle = <0x8>;
  368. phandle = <0x8>;
  369.  
  370. uart {
  371. ralink,group = "uartlite";
  372. ralink,function = "uartlite";
  373. };
  374. };
  375.  
  376. mdio {
  377.  
  378. mdio {
  379. ralink,group = "mdio";
  380. ralink,function = "mdio";
  381. };
  382. };
  383.  
  384. mdio_refclk {
  385.  
  386. mdio_refclk {
  387. ralink,group = "mdio";
  388. ralink,function = "refclk";
  389. };
  390. };
  391.  
  392. ephy {
  393.  
  394. ephy {
  395. ralink,group = "ephy";
  396. ralink,function = "ephy";
  397. };
  398. };
  399.  
  400. wled {
  401.  
  402. wled {
  403. ralink,group = "wled";
  404. ralink,function = "wled";
  405. };
  406. };
  407.  
  408. rgmii1 {
  409.  
  410. rgmii1 {
  411. ralink,group = "rgmii1";
  412. ralink,function = "rgmii1";
  413. };
  414. };
  415.  
  416. rgmii2 {
  417.  
  418. rgmii2 {
  419. ralink,group = "rgmii2";
  420. ralink,function = "rgmii2";
  421. };
  422. };
  423.  
  424. pcie {
  425. linux,phandle = <0x10>;
  426. phandle = <0x10>;
  427.  
  428. pcie {
  429. ralink,group = "pcie";
  430. ralink,function = "pcie rst";
  431. };
  432. };
  433.  
  434. pa {
  435.  
  436. pa {
  437. ralink,group = "pa";
  438. ralink,function = "pa";
  439. };
  440. };
  441.  
  442. sdhci {
  443. linux,phandle = <0xe>;
  444. phandle = <0xe>;
  445.  
  446. sdhci {
  447. ralink,group = "nd_sd";
  448. ralink,function = "sd";
  449. };
  450. };
  451. };
  452.  
  453. rstctrl {
  454. compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
  455. #reset-cells = <0x1>;
  456. linux,phandle = <0x2>;
  457. phandle = <0x2>;
  458. };
  459.  
  460. clkctrl {
  461. compatible = "ralink,rt2880-clock";
  462. #clock-cells = <0x1>;
  463. linux,phandle = <0xb>;
  464. phandle = <0xb>;
  465. };
  466.  
  467. usbphy {
  468. compatible = "mediatek,mt7620-usbphy";
  469. #phy-cells = <0x0>;
  470. ralink,sysctl = <0xa>;
  471. resets = <0x2 0x16 0x2 0x19>;
  472. reset-names = "host", "device";
  473. clocks = <0xb 0x16 0xb 0x19>;
  474. clock-names = "host", "device";
  475. linux,phandle = <0xf>;
  476. phandle = <0xf>;
  477. };
  478.  
  479. ethernet@10100000 {
  480. compatible = "mediatek,mt7620-eth";
  481. reg = <0x10100000 0x10000>;
  482. #address-cells = <0x1>;
  483. #size-cells = <0x0>;
  484. interrupt-parent = <0x3>;
  485. interrupts = <0x5>;
  486. resets = <0x2 0x15 0x2 0x17>;
  487. reset-names = "fe", "esw";
  488. mediatek,switch = <0xc>;
  489. status = "okay";
  490. mtd-mac-address = <0xd 0x4>;
  491. mediatek,portmap = "wllll";
  492.  
  493. port@0 {
  494. compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
  495. reg = <0x0>;
  496. status = "disabled";
  497. };
  498.  
  499. port@5 {
  500. compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
  501. reg = <0x5>;
  502. status = "disabled";
  503. };
  504.  
  505. mdio-bus {
  506. #address-cells = <0x1>;
  507. #size-cells = <0x0>;
  508. status = "disabled";
  509. };
  510. };
  511.  
  512. gsw@10110000 {
  513. compatible = "mediatek,mt7620-gsw";
  514. reg = <0x10110000 0x8000>;
  515. resets = <0x2 0x17>;
  516. reset-names = "esw";
  517. interrupt-parent = <0x1>;
  518. interrupts = <0x11>;
  519. linux,phandle = <0xc>;
  520. phandle = <0xc>;
  521. };
  522.  
  523. sdhci@10130000 {
  524. compatible = "ralink,mt7620-sdhci";
  525. reg = <0x10130000 0x4000>;
  526. interrupt-parent = <0x1>;
  527. interrupts = <0xe>;
  528. pinctrl-names = "default";
  529. pinctrl-0 = <0xe>;
  530. status = "disabled";
  531. };
  532.  
  533. ehci@101c0000 {
  534. #address-cells = <0x1>;
  535. #size-cells = <0x0>;
  536. compatible = "generic-ehci";
  537. reg = <0x101c0000 0x1000>;
  538. interrupt-parent = <0x1>;
  539. interrupts = <0x12>;
  540. phys = <0xf>;
  541. phy-names = "usb";
  542. status = "okay";
  543.  
  544. port@1 {
  545. reg = <0x1>;
  546. #trigger-source-cells = <0x0>;
  547. linux,phandle = <0x13>;
  548. phandle = <0x13>;
  549. };
  550. };
  551.  
  552. ohci@101c1000 {
  553. #address-cells = <0x1>;
  554. #size-cells = <0x0>;
  555. compatible = "generic-ohci";
  556. reg = <0x101c1000 0x1000>;
  557. interrupt-parent = <0x1>;
  558. interrupts = <0x12>;
  559. phys = <0xf>;
  560. phy-names = "usb";
  561. status = "okay";
  562.  
  563. port@1 {
  564. reg = <0x1>;
  565. #trigger-source-cells = <0x0>;
  566. linux,phandle = <0x12>;
  567. phandle = <0x12>;
  568. };
  569. };
  570.  
  571. pcie@10140000 {
  572. compatible = "mediatek,mt7620-pci";
  573. reg = <0x10140000 0x100 0x10142000 0x100>;
  574. #address-cells = <0x3>;
  575. #size-cells = <0x2>;
  576. resets = <0x2 0x1a>;
  577. reset-names = "pcie0";
  578. clocks = <0xb 0x1a>;
  579. clock-names = "pcie0";
  580. interrupt-parent = <0x3>;
  581. interrupts = <0x4>;
  582. pinctrl-names = "default";
  583. pinctrl-0 = <0x10>;
  584. device_type = "pci";
  585. bus-range = <0x0 0xff>;
  586. ranges = <0x2000000 0x0 0x0 0x20000000 0x0 0x10000000 0x1000000 0x0 0x0 0x10160000 0x0 0x10000>;
  587. status = "disabled";
  588.  
  589. pcie@0,0 {
  590. reg = <0x0 0x0 0x0 0x0 0x0>;
  591. #address-cells = <0x3>;
  592. #size-cells = <0x2>;
  593. device_type = "pci";
  594. ranges;
  595. };
  596. };
  597.  
  598. wmac@10180000 {
  599. compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
  600. reg = <0x10180000 0x40000>;
  601. interrupt-parent = <0x3>;
  602. interrupts = <0x6>;
  603. ralink,eeprom = "soc_wmac.eeprom";
  604. };
  605.  
  606. memory@0 {
  607. device_type = "memory";
  608. reg = <0x0 0x4000000>;
  609. };
  610.  
  611. leds {
  612. compatible = "gpio-leds";
  613.  
  614. power {
  615. label = "board:orange:power";
  616. gpios = <0x11 0x9 0x1>;
  617. };
  618.  
  619. wifi {
  620. label = "board:red:wifi";
  621. gpios = <0x14 0x0 0x1>;
  622. linux,default-trigger = "phy0tpt";
  623. };
  624. };
  625.  
  626. keys {
  627. compatible = "gpio-keys-polled";
  628. poll-interval = <0x14>;
  629.  
  630. reset {
  631. label = "reset";
  632. gpios = <0x11 0x1 0x1>;
  633. linux,code = <0x198>;
  634. };
  635. };
  636.  
  637. gpio_export {
  638. compatible = "gpio-export";
  639. #size-cells = <0x0>;
  640.  
  641. enable-leds {
  642. gpio-export,name = "enable-leds";
  643. gpio-export,output = <0x1>;
  644. gpios = <0x11 0xa 0x0>;
  645. };
  646. };
  647. };
  648.  
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