LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY led_rand IS
--	 generic (N : integer := 1);
	Port(
		input, reset, clk 	: in std_logic;
		led 				: in std_logic_vector(17 downto 0);
		led_out 			: out std_logic_vector(17 downto 0)
	);

end led_rand;

ARCHITECTURE led_mix OF led_rand IS

begin
RANDOM : process(input)
	signal led_tmp : std_logic_vector(17 downto 0) := "000000000000000000";
	begin
	if(reset = '1') then
		led_out <= "000000000000000000";
	elsif(input = '1') then
		for i in 0 to 5 loop
			led_tmp <= led_tmp + led;
		end loop;
		led_out <= led_tmp;
		led_tmp <= "000000000000000000";
	end if;
end process RANDOM;

end led_mix;