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  1. diff -burN orig.gcc-3.2.3/config.sub gcc-3.2.3/config.sub
  2. --- orig.gcc-3.2.3/config.sub 2003-01-30 18:32:36.000000000 -0400
  3. +++ gcc-3.2.3/config.sub 2007-07-26 13:04:40.000000000 -0300
  4. @@ -236,6 +236,7 @@
  5. | i370 | i860 | i960 | ia64 \
  6. | ip2k \
  7. | m32r | m68000 | m68k | m88k | mcore \
  8. + | mips64r5900 | mips64r5900el \
  9. | mips | mipsbe | mipseb | mipsel | mipsle \
  10. | mips16 \
  11. | mips64 | mips64el \
  12. @@ -308,6 +309,7 @@
  13. | m32r-* \
  14. | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
  15. | m88110-* | m88k-* | mcore-* \
  16. + | mips64r5900-* | mips64r5900el-* \
  17. | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
  18. | mips16-* \
  19. | mips64-* | mips64el-* \
  20. @@ -594,6 +596,10 @@
  21. basic_machine=i386-unknown
  22. os=-vsta
  23. ;;
  24. + iop)
  25. + basic_machine=mipsel-scei
  26. + os=-irx
  27. + ;;
  28. iris | iris4d)
  29. basic_machine=mips-sgi
  30. case $os in
  31. @@ -630,6 +636,16 @@
  32. basic_machine=m68k-atari
  33. os=-mint
  34. ;;
  35. + mipsEE* | ee | ps2)
  36. + basic_machine=mips64r5900el-scei
  37. + case $os in
  38. + -linux*)
  39. + ;;
  40. + *)
  41. + os=-elf
  42. + ;;
  43. + esac
  44. + ;;
  45. mips3*-*)
  46. basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
  47. ;;
  48. @@ -1118,7 +1134,8 @@
  49. | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \
  50. | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \
  51. | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \
  52. - | -powermax* | -dnix* | -microbsd*)
  53. + | -powermax* | -dnix* | -microbsd* \
  54. + | -irx* )
  55. # Remember, each alternative MUST END IN *, to match a version number.
  56. ;;
  57. -qnx*)
  58. diff -burN orig.gcc-3.2.3/configure gcc-3.2.3/configure
  59. --- orig.gcc-3.2.3/configure 2002-06-24 13:14:28.000000000 -0300
  60. +++ gcc-3.2.3/configure 2007-07-26 13:04:40.000000000 -0300
  61. @@ -89,7 +89,7 @@
  62. target_alias=NOTARGET
  63. target_makefile_frag=
  64. undefs=NOUNDEFS
  65. -version="$Revision: 1.40.6.3 $"
  66. +version="$Revision: 1.8 $"
  67. x11=default
  68. bindir='${exec_prefix}/bin'
  69. sbindir='${exec_prefix}/sbin'
  70. @@ -697,7 +697,7 @@
  71. if test -f skip-this-dir; then
  72. # Perform the same cleanup as the trap handler, minus the "exit 1" of course,
  73. # and reset the trap handler.
  74. - trap 0
  75. + trap - 0
  76. rm -rf Makefile* ${tmpdir}
  77. # Execute the final clean-up actions
  78. ${config_shell} skip-this-dir
  79. @@ -1615,7 +1615,7 @@
  80. # Perform the same cleanup as the trap handler, minus the "exit 1" of course,
  81. # and reset the trap handler.
  82. rm -rf ${tmpdir}
  83. -trap 0
  84. +trap - 0
  85.  
  86. exit 0
  87.  
  88. diff -burN orig.gcc-3.2.3/configure.in gcc-3.2.3/configure.in
  89. --- orig.gcc-3.2.3/configure.in 2002-07-08 07:00:57.000000000 -0300
  90. +++ gcc-3.2.3/configure.in 2007-07-26 13:04:40.000000000 -0300
  91. @@ -980,6 +980,9 @@
  92. mips*-*-linux*)
  93. noconfigdirs="$noconfigdirs target-libffi"
  94. ;;
  95. + mipsel-*-irx*)
  96. + noconfigdirs="$noconfigdirs target-libiberty target-newlib target-libgloss target-libstdc++-v3 ${libgcj}"
  97. + ;;
  98. mips*-*-*)
  99. noconfigdirs="$noconfigdirs gprof ${libgcj}"
  100. ;;
  101. diff -burN orig.gcc-3.2.3/gcc/caller-save.c gcc-3.2.3/gcc/caller-save.c
  102. --- orig.gcc-3.2.3/gcc/caller-save.c 2002-01-01 18:22:25.000000000 -0400
  103. +++ gcc-3.2.3/gcc/caller-save.c 2007-07-26 13:04:40.000000000 -0300
  104. @@ -50,13 +50,21 @@
  105. If that is not possible the save is done one register at a time. */
  106.  
  107. static enum machine_mode
  108. +#if TARGET_MIPS5900
  109. + regno_save_mode[FIRST_PSEUDO_REGISTER][16 / MIN_UNITS_PER_WORD + 1];
  110. +#else
  111. regno_save_mode[FIRST_PSEUDO_REGISTER][MAX_MOVE_MAX / MIN_UNITS_PER_WORD + 1];
  112. +#endif
  113.  
  114. /* For each hard register, a place on the stack where it can be saved,
  115. if needed. */
  116.  
  117. static rtx
  118. +#if TARGET_MIPS5900
  119. + regno_save_mem[FIRST_PSEUDO_REGISTER][16 / MIN_UNITS_PER_WORD + 1];
  120. +#else
  121. regno_save_mem[FIRST_PSEUDO_REGISTER][MAX_MOVE_MAX / MIN_UNITS_PER_WORD + 1];
  122. +#endif
  123.  
  124. /* We will only make a register eligible for caller-save if it can be
  125. saved in its widest mode with a simple SET insn as long as the memory
  126. diff -burN orig.gcc-3.2.3/gcc/c-common.c gcc-3.2.3/gcc/c-common.c
  127. --- orig.gcc-3.2.3/gcc/c-common.c 2002-12-01 14:19:08.000000000 -0400
  128. +++ gcc-3.2.3/gcc/c-common.c 2007-07-26 13:04:40.000000000 -0300
  129. @@ -1336,6 +1336,9 @@
  130. if (bits <= TYPE_PRECISION (intDI_type_node))
  131. return unsignedp ? unsigned_intDI_type_node : intDI_type_node;
  132.  
  133. + if (bits <= TYPE_PRECISION (intTI_type_node))
  134. + return unsignedp ? unsigned_intTI_type_node : intTI_type_node;
  135. +
  136. return 0;
  137. }
  138.  
  139. @@ -1379,10 +1382,8 @@
  140. if (mode == DImode)
  141. return unsignedp ? unsigned_intDI_type_node : intDI_type_node;
  142.  
  143. -#if HOST_BITS_PER_WIDE_INT >= 64
  144. if (mode == TYPE_MODE (intTI_type_node))
  145. return unsignedp ? unsigned_intTI_type_node : intTI_type_node;
  146. -#endif
  147.  
  148. if (mode == TYPE_MODE (float_type_node))
  149. return float_type_node;
  150. @@ -1449,10 +1450,8 @@
  151. return long_long_unsigned_type_node;
  152. if (type1 == widest_integer_literal_type_node)
  153. return widest_unsigned_literal_type_node;
  154. -#if HOST_BITS_PER_WIDE_INT >= 64
  155. if (type1 == intTI_type_node)
  156. return unsigned_intTI_type_node;
  157. -#endif
  158. if (type1 == intDI_type_node)
  159. return unsigned_intDI_type_node;
  160. if (type1 == intSI_type_node)
  161. @@ -1484,10 +1483,8 @@
  162. return long_long_integer_type_node;
  163. if (type1 == widest_unsigned_literal_type_node)
  164. return widest_integer_literal_type_node;
  165. -#if HOST_BITS_PER_WIDE_INT >= 64
  166. if (type1 == unsigned_intTI_type_node)
  167. return intTI_type_node;
  168. -#endif
  169. if (type1 == unsigned_intDI_type_node)
  170. return intDI_type_node;
  171. if (type1 == unsigned_intSI_type_node)
  172. @@ -1527,10 +1524,8 @@
  173. return (unsignedp ? widest_unsigned_literal_type_node
  174. : widest_integer_literal_type_node);
  175.  
  176. -#if HOST_BITS_PER_WIDE_INT >= 64
  177. if (TYPE_PRECISION (type) == TYPE_PRECISION (intTI_type_node))
  178. return unsignedp ? unsigned_intTI_type_node : intTI_type_node;
  179. -#endif
  180. if (TYPE_PRECISION (type) == TYPE_PRECISION (intDI_type_node))
  181. return unsignedp ? unsigned_intDI_type_node : intDI_type_node;
  182. if (TYPE_PRECISION (type) == TYPE_PRECISION (intSI_type_node))
  183. @@ -2576,16 +2571,12 @@
  184. pushdecl (build_decl (TYPE_DECL, NULL_TREE, intHI_type_node));
  185. pushdecl (build_decl (TYPE_DECL, NULL_TREE, intSI_type_node));
  186. pushdecl (build_decl (TYPE_DECL, NULL_TREE, intDI_type_node));
  187. -#if HOST_BITS_PER_WIDE_INT >= 64
  188. pushdecl (build_decl (TYPE_DECL, get_identifier ("__int128_t"), intTI_type_node));
  189. -#endif
  190. pushdecl (build_decl (TYPE_DECL, NULL_TREE, unsigned_intQI_type_node));
  191. pushdecl (build_decl (TYPE_DECL, NULL_TREE, unsigned_intHI_type_node));
  192. pushdecl (build_decl (TYPE_DECL, NULL_TREE, unsigned_intSI_type_node));
  193. pushdecl (build_decl (TYPE_DECL, NULL_TREE, unsigned_intDI_type_node));
  194. -#if HOST_BITS_PER_WIDE_INT >= 64
  195. pushdecl (build_decl (TYPE_DECL, get_identifier ("__uint128_t"), unsigned_intTI_type_node));
  196. -#endif
  197.  
  198. /* Create the widest literal types. */
  199. widest_integer_literal_type_node
  200. diff -burN orig.gcc-3.2.3/gcc/config/i386/xm-mingw32.h gcc-3.2.3/gcc/config/i386/xm-mingw32.h
  201. --- orig.gcc-3.2.3/gcc/config/i386/xm-mingw32.h 2002-01-10 18:21:39.000000000 -0400
  202. +++ gcc-3.2.3/gcc/config/i386/xm-mingw32.h 2007-07-26 13:04:51.000000000 -0300
  203. @@ -31,3 +31,143 @@
  204.  
  205. #undef PATH_SEPARATOR
  206. #define PATH_SEPARATOR ';'
  207. +
  208. +/* This describes the machine the compiler is hosted on. */
  209. +#define HOST_BITS_PER_CHAR CHAR_BIT
  210. +#define HOST_BITS_PER_SHORT (CHAR_BIT * SIZEOF_SHORT)
  211. +#define HOST_BITS_PER_INT (CHAR_BIT * SIZEOF_INT)
  212. +#define HOST_BITS_PER_LONG (CHAR_BIT * SIZEOF_LONG)
  213. +
  214. +#ifdef HAVE_LONG_LONG
  215. +# define HOST_BITS_PER_LONGLONG (CHAR_BIT * SIZEOF_LONG_LONG)
  216. +#else
  217. +#ifdef HAVE___INT64
  218. +# define HOST_BITS_PER_LONGLONG (CHAR_BIT * SIZEOF___INT64)
  219. +#else
  220. +/* If we're here and we're GCC, assume this is stage 2+ of a bootstrap
  221. + and 'long long' has the width of the *target*'s long long. */
  222. +# if GCC_VERSION > 3000
  223. +# define HOST_BITS_PER_LONGLONG LONG_LONG_TYPE_SIZE
  224. +# endif /* gcc */
  225. +#endif
  226. +#endif /* no long long */
  227. +
  228. +/* Find the largest host integer type and set its size and type. */
  229. +
  230. +/* Use long long on the host if the target has a wider long type than
  231. + the host. */
  232. +
  233. +#if ! defined HOST_BITS_PER_WIDE_INT \
  234. + && defined HOST_BITS_PER_LONGLONG \
  235. + && (HOST_BITS_PER_LONGLONG > HOST_BITS_PER_LONG) \
  236. + && (defined (LONG_LONG_MAX) || defined (LONGLONG_MAX) \
  237. + || defined (LLONG_MAX) || defined (__GNUC__))
  238. +
  239. +# ifdef MAX_LONG_TYPE_SIZE
  240. +# if MAX_LONG_TYPE_SIZE > HOST_BITS_PER_LONG
  241. +# define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONGLONG
  242. +# define HOST_WIDE_INT long long
  243. +# endif
  244. +# else
  245. +# if LONG_TYPE_SIZE > HOST_BITS_PER_LONG
  246. +# define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONGLONG
  247. +# define HOST_WIDE_INT long long
  248. +# endif
  249. +# endif
  250. +
  251. +#endif
  252. +
  253. +#ifndef HOST_BITS_PER_WIDE_INT
  254. +
  255. +# if HOST_BITS_PER_LONG > HOST_BITS_PER_INT
  256. +# define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONG
  257. +# define HOST_WIDE_INT long
  258. +# else
  259. +# define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_INT
  260. +# define HOST_WIDE_INT int
  261. +# endif
  262. +
  263. +#endif /* ! HOST_BITS_PER_WIDE_INT */
  264. +
  265. +/* Provide defaults for the way to print a HOST_WIDE_INT
  266. + in various manners. */
  267. +
  268. +#ifndef HOST_WIDE_INT_PRINT_DEC
  269. +# if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
  270. +# define HOST_WIDE_INT_PRINT_DEC "%d"
  271. +# else
  272. +# if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_LONG
  273. +# define HOST_WIDE_INT_PRINT_DEC "%ld"
  274. +# else
  275. +# define HOST_WIDE_INT_PRINT_DEC "%I64d"
  276. +# endif
  277. +# endif
  278. +#endif /* ! HOST_WIDE_INT_PRINT_DEC */
  279. +
  280. +#ifndef HOST_WIDE_INT_PRINT_UNSIGNED
  281. +# if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
  282. +# define HOST_WIDE_INT_PRINT_UNSIGNED "%u"
  283. +# else
  284. +# if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_LONG
  285. +# define HOST_WIDE_INT_PRINT_UNSIGNED "%lu"
  286. +# else
  287. +# define HOST_WIDE_INT_PRINT_UNSIGNED "%I64u"
  288. +# endif
  289. +# endif
  290. +#endif /* ! HOST_WIDE_INT_PRINT_UNSIGNED */
  291. +
  292. +#ifndef HOST_WIDE_INT_PRINT_HEX
  293. +# if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
  294. +# define HOST_WIDE_INT_PRINT_HEX "0x%x"
  295. +# else
  296. +# if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_LONG
  297. +# define HOST_WIDE_INT_PRINT_HEX "0x%lx"
  298. +# else
  299. +# define HOST_WIDE_INT_PRINT_HEX "0x%I64x"
  300. +# endif
  301. +# endif
  302. +#endif /* ! HOST_WIDE_INT_PRINT_HEX */
  303. +
  304. +#ifndef HOST_WIDE_INT_PRINT_DOUBLE_HEX
  305. +# if HOST_BITS_PER_WIDE_INT == 64
  306. +# if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
  307. +# define HOST_WIDE_INT_PRINT_DOUBLE_HEX "0x%x%016x"
  308. +# else
  309. +# if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_LONG
  310. +# define HOST_WIDE_INT_PRINT_DOUBLE_HEX "0x%lx%016lx"
  311. +# else
  312. +# define HOST_WIDE_INT_PRINT_DOUBLE_HEX "0x%llx%016llx"
  313. +# endif
  314. +# endif
  315. +# else
  316. +# if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
  317. +# define HOST_WIDE_INT_PRINT_DOUBLE_HEX "0x%x%08x"
  318. +# else
  319. +# if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_LONG
  320. +# define HOST_WIDE_INT_PRINT_DOUBLE_HEX "0x%lx%08lx"
  321. +# else
  322. +# define HOST_WIDE_INT_PRINT_DOUBLE_HEX "0x%llx%08llx"
  323. +# endif
  324. +# endif
  325. +# endif
  326. +#endif /* ! HOST_WIDE_INT_PRINT_DOUBLE_HEX */
  327. +
  328. +/* Find HOST_WIDEST_INT and set its bit size, type and print macros.
  329. + It will be the largest integer mode supported by the host which may
  330. + (or may not) be larger than HOST_WIDE_INT. */
  331. +
  332. +#ifndef HOST_WIDEST_INT
  333. +#if defined HOST_BITS_PER_LONGLONG && HOST_BITS_PER_LONGLONG > HOST_BITS_PER_LONG
  334. +# define HOST_BITS_PER_WIDEST_INT HOST_BITS_PER_LONGLONG
  335. +# define HOST_WIDEST_INT __int64
  336. +# define HOST_WIDEST_INT_PRINT_DEC "%I64d"
  337. +# define HOST_WIDEST_INT_PRINT_UNSIGNED "%I64u"
  338. +# define HOST_WIDEST_INT_PRINT_HEX "0x%I64x"
  339. +# else
  340. +# define HOST_BITS_PER_WIDEST_INT HOST_BITS_PER_LONG
  341. +# define HOST_WIDEST_INT long
  342. +# define HOST_WIDEST_INT_PRINT_DEC "%ld"
  343. +# define HOST_WIDEST_INT_PRINT_UNSIGNED "%lu"
  344. +# define HOST_WIDEST_INT_PRINT_HEX "0x%lx"
  345. +# endif /* long long wider than long */
  346. +#endif /* ! HOST_WIDEST_INT */
  347. diff -burN orig.gcc-3.2.3/gcc/config/mips/core-mmi.h gcc-3.2.3/gcc/config/mips/core-mmi.h
  348. --- orig.gcc-3.2.3/gcc/config/mips/core-mmi.h 1969-12-31 20:00:00.000000000 -0400
  349. +++ gcc-3.2.3/gcc/config/mips/core-mmi.h 2007-07-26 13:04:40.000000000 -0300
  350. @@ -0,0 +1,104 @@
  351. +/*
  352. + * mmi-intrinsics.h - R5900 MMI compiler intrinsics.
  353. + *
  354. + * Copyright (c) 2003 M. R. Brown <mrbrown@0xd6.org>
  355. + *
  356. + * This file is licensed under the GNU GPL version 2.
  357. + *
  358. + * As a special exception, if you include this header file into source
  359. + * files compiled by GCC, this header file does not by itself cause
  360. + * the resulting executable to be covered by the GNU General Public
  361. + * License. This exception does not however invalidate any other
  362. + * reasons why the executable file might be covered by the GNU General
  363. + * Public License.
  364. + *
  365. + */
  366. +
  367. +/* Based off of the mmintrin.h file in GCC 3.2.1 */
  368. +
  369. +#ifndef __mmi_intrinsics_h
  370. +#define __mmi_intrinsics_h
  371. +
  372. +/* This for user programs. */
  373. +typedef int __m128 __attribute__ ((mode(TI)));
  374. +
  375. +#define __vector __attribute__((vector_size(16)))
  376. +
  377. +/* These are internal. */
  378. +typedef int __v16qi __attribute__ ((mode(V16QI)));
  379. +typedef int __v8hi __attribute__ ((mode(V8HI)));
  380. +typedef int __v4si __attribute__ ((mode(V4SI)));
  381. +
  382. +#if !defined(__u128)
  383. +typedef unsigned int __u128 __attribute__((mode(TI)));
  384. +#endif
  385. +#if !defined(__s128)
  386. +typedef __signed__ int __s128 __attribute__((mode(TI)));
  387. +#endif
  388. +
  389. +/* Convert i to a __m128 object. The integer is zero-extended to 128-bits. */
  390. +/* XXX: No, not really. Figure out why. */
  391. +static __inline __m128 _mmi_cvtsi32_si128(int i)
  392. +{
  393. + __u128 tmp = (unsigned int)i;
  394. + return (__m128)tmp;
  395. +}
  396. +
  397. +/* Add the 8-bit values in m1 to the 8-bit values in m2. */
  398. +
  399. +static inline __m128
  400. +_mmi_paddb(__m128 m1, __m128 m2)
  401. +{
  402. + return (__m128) __builtin_mmi_paddb((__v16qi)m1, (__v16qi)m2);
  403. +}
  404. +
  405. +/* Creates a vector of two 64-bit values; d0 is least significant. */
  406. +static inline __m128
  407. +_mmi_create_vec64(long d1, long d0)
  408. +{
  409. + union {
  410. + __m128 q;
  411. + struct {
  412. + unsigned long d0;
  413. + unsigned long d1;
  414. + } s;
  415. + } u;
  416. +
  417. + u.s.d0 = d0;
  418. + u.s.d1 = d1;
  419. + return u.q;
  420. +}
  421. +
  422. +/* Convienence routines for creating vectors. */
  423. +
  424. +/* Creates a vector of 4 32-bit values; w0 is least significant. */
  425. +static inline __m128
  426. +_mmi_create_vec32(int w3, int w2, int w1, int w0)
  427. +{
  428. + unsigned long d1 = (unsigned int)w3 << 32 | (unsigned int)w2;
  429. + unsigned long d0 = (unsigned int)w1 << 32 | (unsigned int)w0;
  430. + return _mmi_create_vec64(d1, d0);
  431. +}
  432. +
  433. +/* Creates a vector of 8 16-bit values; h0 is least significant. */
  434. +static inline __m128
  435. +_mmi_create_vec16(short h7, short h6, short h5, short h4,
  436. + short h3, short h2, short h1, short h0)
  437. +{
  438. + unsigned long d1, d0;
  439. +
  440. + d1 = (unsigned short)h7;
  441. + d1 = d1 << 16 | (unsigned short)h6;
  442. + d1 = d1 << 16 | (unsigned short)h5;
  443. + d1 = d1 << 16 | (unsigned short)h4;
  444. +
  445. + d0 = (unsigned short)h3;
  446. + d0 = d0 << 16 | (unsigned short)h2;
  447. + d0 = d0 << 16 | (unsigned short)h1;
  448. + d0 = d0 << 16 | (unsigned short)h0;
  449. +
  450. + return _mmi_create_vec64(d1, d0);
  451. +}
  452. +
  453. +#endif /* __mmi_intrinsics_h */
  454. +
  455. diff -burN orig.gcc-3.2.3/gcc/config/mips/core-vumm.h gcc-3.2.3/gcc/config/mips/core-vumm.h
  456. --- orig.gcc-3.2.3/gcc/config/mips/core-vumm.h 1969-12-31 20:00:00.000000000 -0400
  457. +++ gcc-3.2.3/gcc/config/mips/core-vumm.h 2007-07-26 13:04:40.000000000 -0300
  458. @@ -0,0 +1 @@
  459. +#define __THIS__IS__A__BLANK__FILE__
  460. diff -burN orig.gcc-3.2.3/gcc/config/mips/crti5900.asm gcc-3.2.3/gcc/config/mips/crti5900.asm
  461. --- orig.gcc-3.2.3/gcc/config/mips/crti5900.asm 1969-12-31 20:00:00.000000000 -0400
  462. +++ gcc-3.2.3/gcc/config/mips/crti5900.asm 2007-07-26 13:04:40.000000000 -0300
  463. @@ -0,0 +1,16 @@
  464. +/* 4 slots for argument spill area. 1 for cpreturn, 1 for stack.
  465. + Return spill offset of 80. */
  466. +
  467. + .section .init,"ax",@progbits
  468. + .globl _init
  469. + .type _init,@function
  470. +_init:
  471. + addu $sp,$sp,-96
  472. + sq $31,80($sp)
  473. +
  474. + .section .fini,"ax",@progbits
  475. + .globl _fini
  476. + .type _fini,@function
  477. +_fini:
  478. + addu $sp,$sp,-96
  479. + sq $31,80($sp)
  480. diff -burN orig.gcc-3.2.3/gcc/config/mips/crtn5900.asm gcc-3.2.3/gcc/config/mips/crtn5900.asm
  481. --- orig.gcc-3.2.3/gcc/config/mips/crtn5900.asm 1969-12-31 20:00:00.000000000 -0400
  482. +++ gcc-3.2.3/gcc/config/mips/crtn5900.asm 2007-07-26 13:04:40.000000000 -0300
  483. @@ -0,0 +1,12 @@
  484. +/* 4 slots for argument spill area. 1 for cpreturn, 1 for stack.
  485. + Return spill offset of 80. */
  486. +
  487. + .section .init,"ax",@progbits
  488. + lq $31,80($sp)
  489. + addu $sp,$sp,96
  490. + j $31
  491. +
  492. + .section .fini,"ax",@progbits
  493. + lq $31,80($sp)
  494. + addu $sp,$sp,96
  495. + j $31
  496. diff -burN orig.gcc-3.2.3/gcc/config/mips/mips.c gcc-3.2.3/gcc/config/mips/mips.c
  497. --- orig.gcc-3.2.3/gcc/config/mips/mips.c 2002-07-26 20:23:02.000000000 -0300
  498. +++ gcc-3.2.3/gcc/config/mips/mips.c 2015-08-10 16:10:25 +0300
  499. @@ -51,6 +51,7 @@
  500. #include "gstab.h"
  501. #include "hashtab.h"
  502. #include "debug.h"
  503. +#include "optabs.h"
  504. #include "target.h"
  505. #include "target-def.h"
  506.  
  507. @@ -102,6 +103,7 @@
  508. int, int));
  509. static void mips_emit_frame_related_store PARAMS ((rtx, rtx,
  510. HOST_WIDE_INT));
  511. +static void mips_check_reg_mode PARAMS ((rtx, rtx, void *));
  512. static void save_restore_insns PARAMS ((int, rtx,
  513. long, FILE *));
  514. static void mips16_output_gp_offset PARAMS ((FILE *, rtx));
  515. @@ -135,6 +137,23 @@
  516. #endif
  517. static int mips_adjust_cost PARAMS ((rtx, rtx, rtx, int));
  518.  
  519. +/* R5900 (Emotion Engine) support. */
  520. +static enum sequence_type r5900_detect_sequence_type PARAMS ((rtx, int *, rtx *,
  521. + int *, int));
  522. +static void r5900_lengthen_loops PARAMS ((rtx, int));
  523. +static void r5900_sched_init PARAMS ((void));
  524. +static void mips_sched_init PARAMS ((FILE *, int, int));
  525. +static void r5900_sched_reorder PARAMS ((FILE *, int, rtx *, int));
  526. +static int mips_sched_reorder PARAMS ((FILE *, int, rtx *,
  527. + int *, int));
  528. +static void r5900_init_builtins PARAMS ((void));
  529. +static rtx r5900_expand_binop_builtin PARAMS ((enum insn_code, tree,
  530. + rtx));
  531. +static rtx r5900_expand_builtin PARAMS ((tree, rtx));
  532. +static rtx mips_expand_builtin PARAMS ((tree, rtx, rtx,
  533. + enum machine_mode, int));
  534. +static void mips_init_builtins PARAMS ((void));
  535. +
  536. /* Global variables for machine-dependent things. */
  537.  
  538. /* Threshold for data being put into the small data/bss area, instead
  539. @@ -232,6 +251,8 @@
  540. /* which abi to use. */
  541. int mips_abi;
  542.  
  543. +int mips_alignment;
  544. +
  545. /* Strings to hold which cpu and instruction set architecture to use. */
  546. const char *mips_cpu_string; /* for -mcpu=<xxx> */
  547. const char *mips_arch_string; /* for -march=<xxx> */
  548. @@ -253,6 +274,18 @@
  549. set this option if such an option is used. */
  550. const char *mips_explicit_type_size_string;
  551.  
  552. +#ifdef DEFAULT_MIPS_ALIGNMENT
  553. +int mips_alignment=DEFAULT_MIPS_ALIGNMENT; /* biggest alignment bits */
  554. +#else
  555. +int mips_alignment=BIGGEST_ALIGNMENT; /* biggest alignment bits */
  556. +#endif
  557. +const char * mips_no_align128_string;
  558. +const char * mips_align128_string;
  559. +const char * mips_use_128_string;
  560. +const char * mips_align_all_string;
  561. +int mips_align_all = 1;
  562. +int mips_use_128 = 0;
  563. +
  564. /* Whether we are generating mips16 hard float code. In mips16 mode
  565. we always set TARGET_SOFT_FLOAT; this variable is nonzero if
  566. -msoft-float was not specified by the user, which means that we
  567. @@ -280,8 +313,11 @@
  568. initialized in override_options. */
  569. REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
  570.  
  571. -/* Mode used for saving/restoring general purpose registers. */
  572. -static enum machine_mode gpr_mode;
  573. +/* The mode that will be used to save a given gpr on the stack. Note
  574. + the entry for $0 is special; it indicates the generic size of a gpr
  575. + save/restore by the prologue/epilogue and must be the maximum mode
  576. + ever used to save a GPR. This is typically WORD_MODE. */
  577. +enum machine_mode mips_reg_mode[GP_REG_NUM];
  578.  
  579. /* Array giving truth value on whether or not a given hard register
  580. can support a given mode. */
  581. @@ -343,7 +379,8 @@
  582. "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
  583. "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
  584. "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
  585. - "$fcc5","$fcc6","$fcc7","$rap"
  586. + "$fcc5","$fcc6","$fcc7","$rap",
  587. + "hi1", "lo1", "accum1"
  588. };
  589.  
  590. /* Mips software names for the registers, used to overwrite the
  591. @@ -360,7 +397,8 @@
  592. "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
  593. "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
  594. "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
  595. - "$fcc5","$fcc6","$fcc7","$rap"
  596. + "$fcc5","$fcc6","$fcc7","$rap",
  597. + "hi1", "lo1", "accum1"
  598. };
  599.  
  600. /* Map hard register number to register class */
  601. @@ -384,7 +422,8 @@
  602. FP_REGS, FP_REGS, FP_REGS, FP_REGS,
  603. HI_REG, LO_REG, HILO_REG, ST_REGS,
  604. ST_REGS, ST_REGS, ST_REGS, ST_REGS,
  605. - ST_REGS, ST_REGS, ST_REGS, GR_REGS
  606. + ST_REGS, ST_REGS, ST_REGS, GR_REGS,
  607. + HI1_REG, LO1_REG, HILO1_REG
  608. };
  609.  
  610. /* Map register constraint character to register class. */
  611. @@ -479,6 +518,18 @@
  612. #undef TARGET_SCHED_ADJUST_COST
  613. #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
  614.  
  615. +#undef TARGET_SCHED_INIT
  616. +#define TARGET_SCHED_INIT mips_sched_init
  617. +
  618. +#undef TARGET_SCHED_REORDER
  619. +#define TARGET_SCHED_REORDER mips_sched_reorder
  620. +
  621. +#undef TARGET_INIT_BUILTINS
  622. +#define TARGET_INIT_BUILTINS mips_init_builtins
  623. +
  624. +#undef TARGET_EXPAND_BUILTIN
  625. +#define TARGET_EXPAND_BUILTIN mips_expand_builtin
  626. +
  627. struct gcc_target targetm = TARGET_INITIALIZER;
  629. /* Return truth value of whether OP can be used as an operands
  630. @@ -1111,6 +1162,38 @@
  631. && ! mips16_constant (op, mode, 1, 0)));
  632. }
  633.  
  634. +/* Return truth value of whether OP is a register, a memory operand,
  635. + or a constant. This is used by the r5900 lq/sq support. */
  636. +
  637. +int
  638. +movti_operand (op, mode)
  639. + rtx op;
  640. + enum machine_mode mode;
  641. +{
  642. + switch (GET_CODE (op))
  643. + {
  644. + case CONST_INT:
  645. + if (TARGET_MIPS16)
  646. + return FALSE;
  647. + return TRUE;
  648. +
  649. + case CONST_DOUBLE:
  650. + if (TARGET_MIPS16 || GET_MODE (op) != VOIDmode)
  651. + return FALSE;
  652. + return TRUE;
  653. +
  654. + case REG:
  655. + case SUBREG:
  656. + return register_operand (op, mode);
  657. +
  658. + case MEM:
  659. + return memory_operand (op, mode);
  660. +
  661. + default:
  662. + return FALSE;
  663. + }
  664. +}
  665. +
  666. /* Like register_operand, but when in 64 bit mode also accept a sign
  667. extend of a 32 bit register, since the value is known to be already
  668. sign extended. */
  669. @@ -1315,6 +1398,7 @@
  670. accept (subreg (const_int)) which will fail to reload. */
  671. if (CONSTANT_ADDRESS_P (xinsn)
  672. && ! (mips_split_addresses && mips_check_split (xinsn, mode))
  673. + && ! (TARGET_MIPS5900 && mode == TImode)
  674. && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
  675. return 1;
  676.  
  677. @@ -1651,7 +1735,7 @@
  678. if (type == DELAY_LOAD || type == DELAY_FCMP)
  679. num_nops = 1;
  680.  
  681. - else if (type == DELAY_HILO)
  682. + else if (type == DELAY_HILO || type == DELAY_HILO1)
  683. num_nops = 2;
  684.  
  685. else
  686. @@ -1663,6 +1747,7 @@
  687. next_insn = NEXT_INSN (next_insn);
  688.  
  689. dslots_load_total += num_nops;
  690. +
  691. if (TARGET_DEBUG_F_MODE
  692. || !optimize
  693. || type == DELAY_NONE
  694. @@ -1701,6 +1786,11 @@
  695. mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
  696. mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
  697. }
  698. + else if (type == DELAY_HILO1)
  699. + {
  700. + mips_load_reg3 = gen_rtx_REG (SImode, MD1_REG_FIRST);
  701. + mips_load_reg4 = gen_rtx_REG (SImode, MD1_REG_FIRST+1);
  702. + }
  703. else
  704. {
  705. mips_load_reg3 = 0;
  706. @@ -1935,6 +2025,15 @@
  707. ret = "mflo\t%0";
  708. }
  709.  
  710. + else if (MD1_REG_P (regno1))
  711. + {
  712. + delay = DELAY_HILO1;
  713. + if (regno1 != HILO1_REGNUM)
  714. + ret = "mf%1\t%0";
  715. + else
  716. + ret = "mflo1\t%0";
  717. + }
  718. +
  719. else if (ST_REG_P (regno1) && ISA_HAS_8CC)
  720. ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
  721.  
  722. @@ -1971,6 +2070,16 @@
  723. }
  724. }
  725.  
  726. + else if (MD1_REG_P (regno0))
  727. + {
  728. + if (GP_REG_P (regno1))
  729. + {
  730. + delay = DELAY_HILO1;
  731. + if (regno0 != HILO1_REGNUM && ! TARGET_MIPS16)
  732. + ret = "mt%0\t%1";
  733. + }
  734. + }
  735. +
  736. else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
  737. {
  738. if (GP_REG_P (regno1))
  739. @@ -2056,6 +2165,12 @@
  740. delay = DELAY_HILO;
  741. ret = "mt%0\t%.";
  742. }
  743. +
  744. + else if (MD1_REG_P (regno0))
  745. + {
  746. + delay = DELAY_HILO1;
  747. + ret = "mt%0\t%.";
  748. + }
  749. }
  750.  
  751. else if (GP_REG_P (regno0))
  752. @@ -2390,6 +2505,20 @@
  753. ret = "mthi\t%M1\n\tmtlo\t%L1";
  754. }
  755.  
  756. + else if (MD1_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
  757. + {
  758. + delay = DELAY_HILO1;
  759. + if (TARGET_64BIT)
  760. + {
  761. + if (regno0 != HILO1_REGNUM)
  762. + ret = "mt%0\t%1";
  763. + else if (regno1 == 0)
  764. + ret = "mtlo%H0\t%.\n\tmthi%H0\t%.";
  765. + }
  766. + else
  767. + ret = "mthi%H0\t%M1\n\tmtlo%H0\t%L1";
  768. + }
  769. +
  770. else if (GP_REG_P (regno0) && MD_REG_P (regno1))
  771. {
  772. delay = DELAY_HILO;
  773. @@ -2402,6 +2531,18 @@
  774. ret = "mfhi\t%M0\n\tmflo\t%L0";
  775. }
  776.  
  777. + else if (GP_REG_P (regno0) && MD1_REG_P (regno1))
  778. + {
  779. + delay = DELAY_HILO1;
  780. + if (TARGET_64BIT)
  781. + {
  782. + if (regno1 != HILO1_REGNUM)
  783. + ret = "mf%1\t%0";
  784. + }
  785. + else
  786. + ret = "mfhi%H1\t%M0\n\tmflo%H1\t%L0";
  787. + }
  788. +
  789. else if (TARGET_64BIT)
  790. ret = "move\t%0,%1";
  791.  
  792. @@ -2507,6 +2648,14 @@
  793. ? "mtlo\t%.\n\tmthi\t%."
  794. : "mt%0\t%.\n");
  795. }
  796. +
  797. + else if (MD1_REG_P (regno0))
  798. + {
  799. + delay = DELAY_HILO1;
  800. + ret = (regno0 == HILO1_REGNUM
  801. + ? "mtlo%H0\t%.\n\tmthi%H0\t%."
  802. + : "mt%0\t%.\n");
  803. + }
  804. }
  805.  
  806. else if (code1 == CONST_INT && GET_MODE (op0) == DImode
  807. @@ -4015,6 +4164,14 @@
  808. cum->gp_reg_found = 1;
  809. cum->arg_words++;
  810. break;
  811. +
  812. + case V16QImode:
  813. + case V8HImode:
  814. + case V4SImode:
  815. + if (! TARGET_MMI)
  816. + abort ();
  817. + cum->gp_reg_found = 1;
  818. + cum->arg_words++;
  819. }
  820. }
  821.  
  822. @@ -4135,6 +4292,15 @@
  823. if (! TARGET_64BIT)
  824. cum->arg_words += (cum->arg_words & 1);
  825. regbase = GP_ARG_FIRST;
  826. + break;
  827. +
  828. + case V4SImode:
  829. + case V8HImode:
  830. + case V16QImode:
  831. + if (! TARGET_MMI)
  832. + abort ();
  833. + regbase = GP_ARG_FIRST;
  834. +
  835. }
  836.  
  837. if (*arg_words >= (unsigned) MAX_ARGS_IN_REGISTERS)
  838. @@ -4311,6 +4477,7 @@
  839. int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
  840. {
  841. if ((mode == BLKmode
  842. + || (mode == TImode && TARGET_MIPS5900)
  843. || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
  844. || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
  845. && cum->arg_words < (unsigned) MAX_ARGS_IN_REGISTERS
  846. @@ -4851,6 +5018,14 @@
  847. target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
  848. #endif
  849.  
  850. + if (mips_align_all_string == 0)
  851. + mips_align_all = 1;
  852. +
  853. + else if (ISDIGIT (*mips_align_all_string))
  854. + {
  855. + mips_align_all = atoi (mips_align_all_string);
  856. + }
  857. +
  858. /* Get the architectural level. */
  859. if (mips_isa_string == 0)
  860. mips_isa = MIPS_ISA_DEFAULT;
  861. @@ -5081,6 +5256,10 @@
  862. }
  863. }
  864.  
  865. + /* Humf... */
  866. + if (mips_arch == PROCESSOR_R3000)
  867. + mips_isa = 1;
  868. +
  869. /* make sure sizes of ints/longs/etc. are ok */
  870. if (! ISA_HAS_64BIT_REGS)
  871. {
  872. @@ -5234,6 +5413,10 @@
  873. mips_char_to_class['l'] = LO_REG;
  874. mips_char_to_class['a'] = HILO_REG;
  875. mips_char_to_class['x'] = MD_REGS;
  876. + mips_char_to_class['u'] = HI1_REG;
  877. + mips_char_to_class['v'] = LO1_REG;
  878. + mips_char_to_class['q'] = HILO1_REG;
  879. + mips_char_to_class['w'] = MD1_REGS;
  880. mips_char_to_class['b'] = ALL_REGS;
  881. mips_char_to_class['y'] = GR_REGS;
  882. mips_char_to_class['z'] = ST_REGS;
  883. @@ -5279,6 +5462,10 @@
  884. || FP_REG_P (regno));
  885. }
  886.  
  887. + /* General registers can hold TImode values on the r5900. */
  888. + else if (GP_REG_P (regno) && mode == TImode && TARGET_MIPS5900)
  889. + temp = 1;
  890. +
  891. else if (GP_REG_P (regno))
  892. temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
  893.  
  894. @@ -5302,6 +5489,12 @@
  895. || (regno == MD_REG_FIRST
  896. && size == 2 * UNITS_PER_WORD)));
  897.  
  898. + else if (MD1_REG_P (regno))
  899. + temp = (class == MODE_INT
  900. + && (size <= UNITS_PER_WORD
  901. + || (regno == MD1_REG_FIRST
  902. + && size == 2 * UNITS_PER_WORD)));
  903. +
  904. else
  905. temp = 0;
  906.  
  907. @@ -5311,9 +5504,18 @@
  908.  
  909. /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
  910. initialized yet, so we can't use that here. */
  911. - gpr_mode = TARGET_64BIT ? DImode : SImode;
  912. + for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
  913. + {
  914. + mips_reg_mode[regno] = TARGET_64BIT ? DImode : SImode;
  915. + }
  916. +
  917. + /* Saves/restores of general purpose registers on the r5900 use
  918. + a mode wider than word_mode. */
  919. + if (TARGET_MIPS5900)
  920. + mips_reg_mode[0] = TImode;
  921.  
  922. /* Provide default values for align_* for 64-bit targets. */
  923. + /* XXX: fix this up for the r5900. */
  924. if (TARGET_64BIT && !TARGET_MIPS16)
  925. {
  926. if (align_loops == 0)
  927. @@ -5324,6 +5526,21 @@
  928. align_functions = 8;
  929. }
  930.  
  931. +#ifdef DEFAULT_MIPS_ALIGNMENT
  932. + if (mips_align128_string != NULL) {
  933. + /* -malign128 */
  934. + mips_alignment=128;
  935. + }
  936. + if (mips_no_align128_string != NULL) {
  937. + /* -mno-align128 */
  938. + mips_alignment=64;
  939. + }
  940. +#endif
  941. +
  942. + if (mips_use_128_string != NULL) {
  943. + mips_use_128=1;
  944. + }
  945. +
  946. /* Register global variables with the garbage collector. */
  947. mips_add_gc_roots ();
  948. }
  949. @@ -5425,6 +5642,7 @@
  950. 'M' print high-order register of double-word register operand.
  951. 'C' print part of opcode for a branch condition.
  952. 'F' print part of opcode for a floating-point branch condition.
  953. + 'H' print the appropiate Integer pipe # for r5900 mult/div instructions.
  954. 'N' print part of opcode for a branch condition, inverted.
  955. 'W' print part of opcode for a floating-point branch condition, inverted.
  956. 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
  957. @@ -5649,7 +5867,17 @@
  958. default:
  959. abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
  960. }
  961. + else if (letter == 'H')
  962. + {
  963. + if (true_regnum (op) >= MD_REG_FIRST
  964. + && true_regnum (op) <= MD_REG_LAST)
  965. + ;
  966. +
  967. + else if (true_regnum (op) >= MD1_REG_FIRST
  968. + && true_regnum (op) <= MD1_REG_LAST)
  969. + fputs ("1", file);
  970.  
  971. + }
  972. else if (letter == 'S')
  973. {
  974. char buffer[100];
  975. @@ -5673,6 +5901,16 @@
  976. fprintf (file, "%s,", reg_names[regnum]);
  977. }
  978.  
  979. + else if ((letter == 'L' || letter == 'M')
  980. + && code == CONST_DOUBLE
  981. + && GET_MODE (op) == VOIDmode)
  982. + {
  983. + if (letter == 'L')
  984. + fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (op));
  985. + else
  986. + fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (op));
  987. + }
  988. +
  989. else if (code == REG || code == SUBREG)
  990. {
  991. register int regnum;
  992. @@ -6144,8 +6382,7 @@
  993. || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
  994. || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
  995. || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
  996. - || (mips_load_reg4 != 0
  997. - && reg_mentioned_p (mips_load_reg4, pattern)))
  998. + || (mips_load_reg4 != 0 && reg_mentioned_p (mips_load_reg4, pattern)))
  999. fputs ("\t#nop\n", asm_out_file);
  1000.  
  1001. else
  1002. @@ -6343,6 +6580,27 @@
  1003. }
  1004. }
  1006. +void
  1007. +mips_declare_object_align (stream, name, init_string, final_string, size, align)
  1008. + FILE *stream;
  1009. + const char *name;
  1010. + const char *init_string;
  1011. + const char *final_string;
  1012. + int size;
  1013. + int align;
  1014. +{
  1015. + fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
  1016. + assemble_name (stream, name);
  1017. + fprintf (stream, final_string, size, align); /* ":\n", ",%u\n", ",%u\n" */
  1018. +
  1019. + if (TARGET_GP_OPT)
  1020. + {
  1021. + tree name_tree = get_identifier (name);
  1022. + TREE_ASM_WRITTEN (name_tree) = 1;
  1023. + }
  1024. +}
  1025. +
  1026. +
  1027. /* Return the bytes needed to compute the frame pointer from the current
  1028. stack pointer.
  1029.  
  1030. @@ -6455,7 +6713,7 @@
  1031. || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
  1032. <= 4))))
  1033. {
  1034. - gp_reg_size += GET_MODE_SIZE (gpr_mode);
  1035. + gp_reg_size += GET_MODE_SIZE (mips_reg_mode[0]);
  1036. mask |= 1L << (regno - GP_REG_FIRST);
  1037.  
  1038. /* The entry and exit pseudo instructions can not save $17
  1039. @@ -6479,7 +6737,7 @@
  1040. regno = EH_RETURN_DATA_REGNO (i);
  1041. if (regno == INVALID_REGNUM)
  1042. break;
  1043. - gp_reg_size += GET_MODE_SIZE (gpr_mode);
  1044. + gp_reg_size += GET_MODE_SIZE (mips_reg_mode[0]);
  1045. mask |= 1L << (regno - GP_REG_FIRST);
  1046. }
  1047. }
  1048. @@ -6561,9 +6819,9 @@
  1049. top of the stack. */
  1050. if (! mips_entry)
  1051. offset = (args_size + extra_size + var_size
  1052. - + gp_reg_size - GET_MODE_SIZE (gpr_mode));
  1053. + + gp_reg_size - GET_MODE_SIZE (mips_reg_mode[0]));
  1054. else
  1055. - offset = total_size - GET_MODE_SIZE (gpr_mode);
  1056. + offset = total_size - GET_MODE_SIZE (mips_reg_mode[0]);
  1057.  
  1058. current_frame_info.gp_sp_offset = offset;
  1059. current_frame_info.gp_save_offset = offset - total_size;
  1060. @@ -6699,6 +6957,24 @@
  1061. mips_annotate_frame_insn (emit_move_insn (mem, reg), dwarf_expr);
  1062. }
  1063.  
  1064. +/* If modifying X uses a larger mode than in mips_reg_mode,
  1065. + indicate that fact by setting mips_reg_mode. */
  1066. +
  1067. +static void
  1068. +mips_check_reg_mode (x, set, data)
  1069. + rtx x;
  1070. + rtx set ATTRIBUTE_UNUSED;
  1071. + void *data ATTRIBUTE_UNUSED;
  1072. +{
  1073. + if (GET_CODE (x) == REG
  1074. + && REGNO (x) <= GP_REG_LAST
  1075. + && (GET_MODE_SIZE (GET_MODE (x))
  1076. + > GET_MODE_SIZE (mips_reg_mode[REGNO (x)])))
  1077. + {
  1078. + mips_reg_mode[REGNO (x)] = GET_MODE (x);
  1079. + }
  1080. +}
  1081. +
  1082. static void
  1083. save_restore_insns (store_p, large_reg, large_offset, file)
  1084. int store_p; /* true if this is prologue */
  1085. @@ -6735,6 +7011,47 @@
  1086. need a nop in the epilog if at least one register is reloaded in
  1087. addition to return address. */
  1088.  
  1089. + if (TARGET_MIPS5900 && store_p)
  1090. + {
  1091. + rtx insn;
  1092. + tree attr;
  1093. +
  1094. + for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
  1095. + {
  1096. + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
  1097. + note_stores (PATTERN (insn), mips_check_reg_mode, NULL);
  1098. + }
  1099. +
  1100. + if ((attr = lookup_attribute
  1101. + ("register_precision", DECL_ATTRIBUTES (current_function_decl)))
  1102. + != 0)
  1103. + for (; attr; attr = TREE_CHAIN (attr))
  1104. + {
  1105. + const char *reg_expr = IDENTIFIER_POINTER (TREE_VALUE (TREE_VALUE (attr)));
  1106. + tree reg_length = TREE_VALUE (TREE_CHAIN (TREE_VALUE (attr)));
  1107. + enum machine_mode mode = VOIDmode;
  1108. + int j;
  1109. + switch (TREE_INT_CST_LOW (reg_length))
  1110. + {
  1111. + case 32:
  1112. + mode= SImode;
  1113. + break;
  1114. + case 64:
  1115. + mode= DImode;
  1116. + break;
  1117. + case 128:
  1118. + mode= TImode;
  1119. + break;
  1120. + }
  1121. +
  1122. + if ((j = decode_reg_name (reg_expr)) >= 0)
  1123. + {
  1124. + if (j != 0)
  1125. + mips_reg_mode[j] = mode;
  1126. + }
  1127. + }
  1128. + }
  1129. +
  1130. /* Save GP registers if needed. */
  1131. if (mask)
  1132. {
  1133. @@ -6747,7 +7064,7 @@
  1134. gp_offset = current_frame_info.gp_sp_offset;
  1135. end_offset
  1136. = gp_offset - (current_frame_info.gp_reg_size
  1137. - - GET_MODE_SIZE (gpr_mode));
  1138. + - GET_MODE_SIZE (mips_reg_mode[0]));
  1139.  
  1140. if (gp_offset < 0 || end_offset < 0)
  1141. internal_error
  1142. @@ -6810,7 +7127,8 @@
  1143. {
  1144. rtx reg_rtx;
  1145. rtx mem_rtx
  1146. - = gen_rtx (MEM, gpr_mode,
  1147. + = gen_rtx (MEM,
  1148. + mips_reg_mode[regno],
  1149. gen_rtx (PLUS, Pmode, base_reg_rtx,
  1150. GEN_INT (gp_offset - base_offset)));
  1151.  
  1152. @@ -6821,23 +7139,24 @@
  1153. $31, so we load $7 instead, and work things out
  1154. in mips_expand_epilogue. */
  1155. if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
  1156. - reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
  1157. + reg_rtx = gen_rtx (REG, mips_reg_mode[7], GP_REG_FIRST + 7);
  1158. /* The mips16 sometimes needs to save $18. */
  1159. else if (TARGET_MIPS16
  1160. && regno != GP_REG_FIRST + 31
  1161. && ! M16_REG_P (regno))
  1162. {
  1163. if (! store_p)
  1164. - reg_rtx = gen_rtx (REG, gpr_mode, 6);
  1165. + reg_rtx = gen_rtx (REG, mips_reg_mode[6], 6);
  1166. else
  1167. {
  1168. - reg_rtx = gen_rtx (REG, gpr_mode, 3);
  1169. + reg_rtx = gen_rtx (REG, mips_reg_mode[3], 3);
  1170. emit_move_insn (reg_rtx,
  1171. - gen_rtx (REG, gpr_mode, regno));
  1172. + gen_rtx (REG, mips_reg_mode[regno],
  1173. + regno));
  1174. }
  1175. }
  1176. else
  1177. - reg_rtx = gen_rtx (REG, gpr_mode, regno);
  1178. + reg_rtx = gen_rtx (REG, mips_reg_mode[regno], regno);
  1179.  
  1180. if (store_p)
  1181. mips_emit_frame_related_store (mem_rtx, reg_rtx, gp_offset);
  1182. @@ -6847,7 +7166,7 @@
  1183. if (TARGET_MIPS16
  1184. && regno != GP_REG_FIRST + 31
  1185. && ! M16_REG_P (regno))
  1186. - emit_move_insn (gen_rtx (REG, gpr_mode, regno),
  1187. + emit_move_insn (gen_rtx (REG, mips_reg_mode[regno], regno),
  1188. reg_rtx);
  1189. }
  1190. }
  1191. @@ -6889,13 +7208,13 @@
  1192. fprintf (file, "\tmove\t%s,%s\n",
  1193. reg_names[regno], reg_names[r]);
  1194. }
  1195. - gp_offset -= GET_MODE_SIZE (gpr_mode);
  1196. + gp_offset -= GET_MODE_SIZE (mips_reg_mode[0]);
  1197. }
  1198. /* If the restore is being supressed, still take into account
  1199. the offset at which it is stored. */
  1200. else if (BITSET_P (real_mask, regno - GP_REG_FIRST))
  1201. {
  1202. - gp_offset -= GET_MODE_SIZE (gpr_mode);
  1203. + gp_offset -= GET_MODE_SIZE (mips_reg_mode[0]);
  1204. }
  1205. }
  1206. else
  1207. @@ -6920,13 +7239,13 @@
  1208. base_reg_rtx = stack_pointer_rtx, base_offset = 0;
  1209.  
  1210. else if (base_reg_rtx != 0
  1211. - && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
  1212. - && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
  1213. + && (((unsigned HOST_WIDE_INT) (base_offset - fp_offset)) < 32768)
  1214. + && (((unsigned HOST_WIDE_INT) (base_offset - end_offset)) < 32768))
  1215. ; /* already set up for gp registers above */
  1216.  
  1217. else if (large_reg != 0
  1218. - && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
  1219. - && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
  1220. + && (((unsigned HOST_WIDE_INT) (large_offset - fp_offset)) < 32768)
  1221. + && (((unsigned HOST_WIDE_INT) (large_offset - end_offset)) < 32768))
  1222. {
  1223. base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
  1224. base_offset = large_offset;
  1225. @@ -7358,10 +7677,10 @@
  1226. {
  1227. if (offset != 0)
  1228. ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
  1229. - emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
  1230. - gen_rtx (REG, gpr_mode, regno));
  1231. + emit_move_insn (gen_rtx (MEM, mips_reg_mode[regno], ptr),
  1232. + gen_rtx (REG, mips_reg_mode[regno], regno));
  1233.  
  1234. - offset += GET_MODE_SIZE (gpr_mode);
  1235. + offset += GET_MODE_SIZE (mips_reg_mode[0]);
  1236. }
  1237. }
  1238.  
  1239. @@ -7406,7 +7725,8 @@
  1240. moment. */
  1241. if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
  1242. {
  1243. - rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
  1244. + rtx reg_rtx = gen_rtx (REG, mips_reg_mode[GP_REG_FIRST + 3],
  1245. + GP_REG_FIRST + 3);
  1246. long gp_offset, base_offset;
  1247.  
  1248. gp_offset = current_frame_info.gp_sp_offset;
  1249. @@ -7422,8 +7742,9 @@
  1250. base_offset = 0;
  1251. start_sequence ();
  1252. emit_move_insn (reg_rtx,
  1253. - gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
  1254. - emit_move_insn (gen_rtx (MEM, gpr_mode,
  1255. + gen_rtx (REG, mips_reg_mode[GP_REG_FIRST + 18],
  1256. + GP_REG_FIRST + 18));
  1257. + emit_move_insn (gen_rtx (MEM, mips_reg_mode[GP_REG_FIRST + 18],
  1258. gen_rtx (PLUS, Pmode, stack_pointer_rtx,
  1259. GEN_INT (gp_offset
  1260. - base_offset))),
  1261. @@ -8153,6 +8474,11 @@
  1262. if (type == NULL_TREE || mode == DImode || mode == DFmode)
  1263. return 0;
  1264.  
  1265. + /* The r5900 can pass TImode values in a single register, so
  1266. + there is no need to pass it by reference. */
  1267. + if (mode == TImode && TARGET_MIPS5900)
  1268. + return 0;
  1269. +
  1270. size = int_size_in_bytes (type);
  1271. return size == -1 || size > UNITS_PER_WORD;
  1272. }
  1273. @@ -8213,15 +8539,30 @@
  1274. && gp_reg_p
  1275. && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
  1276. ? NO_REGS : gr_regs);
  1277. +
  1278. + else if (class == HILO1_REG && regno != GP_REG_FIRST + 0)
  1279. + return ((! in_p
  1280. + && gp_reg_p
  1281. + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
  1282. + ? NO_REGS : gr_regs);
  1283. +
  1284. else if (regno == HILO_REGNUM)
  1285. return ((in_p
  1286. && class == gr_regs
  1287. && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
  1288. ? NO_REGS : gr_regs);
  1289.  
  1290. + else if (regno == HILO1_REGNUM)
  1291. + return ((in_p
  1292. + && class == gr_regs
  1293. + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
  1294. + ? NO_REGS : gr_regs);
  1295. +
  1296. /* Copying from HI or LO to anywhere other than a general register
  1297. requires a general register. */
  1298. - if (class == HI_REG || class == LO_REG || class == MD_REGS)
  1299. +
  1300. + if (class == HI_REG || class == LO_REG || class == MD_REGS
  1301. + || class == HI1_REG || class == LO1_REG || class == MD1_REGS)
  1302. {
  1303. if (TARGET_MIPS16 && in_p)
  1304. {
  1305. @@ -8230,7 +8571,8 @@
  1306. }
  1307. return gp_reg_p ? NO_REGS : gr_regs;
  1308. }
  1309. - if (MD_REG_P (regno))
  1310. +
  1311. + if (MD_REG_P (regno) || MD1_REG_P (regno))
  1312. {
  1313. if (TARGET_MIPS16 && ! in_p)
  1314. {
  1315. @@ -9389,6 +9731,11 @@
  1316. if (! TARGET_MIPS16)
  1317. return;
  1318.  
  1319. +#ifdef FILL_BDSLOT_WITH_NOP
  1320. + if (TARGET_MIPS5900 && !TARGET_NO_LENGTHEN_LOOP)
  1321. + r5900_lengthen_loops (first,0);
  1322. +#endif
  1323. +
  1324. /* If $gp is used, try to remove stores, and replace loads with
  1325. copies from $gp. */
  1326. if (optimize)
  1327. @@ -9578,6 +9925,205 @@
  1328. constant table, but we have no way to prevent that. */
  1329. }
  1330.  
  1331. +
  1332. +/* On the R5900, we must ensure that the compiler never generates loops
  1333. + that satisfy all of the following conditions:
  1334. +
  1335. + * a loop consists of less than equal to six instructions (including the
  1336. + branch delay slot).
  1337. +
  1338. + * a loop contains only one conditional branch instruction at the
  1339. + end of the loop.
  1340. +
  1341. + * a loop does not contain any other branch or jump instructions.
  1342. +
  1343. + * a branch delay slot of the loop is not nop. ( EE#2.9 or later )
  1344. +
  1345. + We need to do this because of a bug in the chip.
  1346. +
  1347. + */
  1348. +
  1349. +#define NOP_INSN_P(INSN) (rtx_equal_p (INSN, gen_nop ()))
  1350. +
  1351. +enum sequence_type {Jump, Reset, Other};
  1352. +
  1353. +/* Detect if possible loop jump presents in the sequence */
  1354. +
  1355. +static enum sequence_type
  1356. +r5900_detect_sequence_type (insn, count_p, jump_insn_p, seen_before,
  1357. + after_delayed_branch_sched)
  1358. + rtx insn;
  1359. + int *count_p;
  1360. + rtx *jump_insn_p;
  1361. + int *seen_before;
  1362. + int after_delayed_branch_sched;
  1363. +{
  1364. + int i;
  1365. + int detect_later = 0;
  1366. +
  1367. + for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
  1368. + {
  1369. + rtx v_insn;
  1370. + v_insn = XVECEXP (PATTERN (insn), 0, i);
  1371. +
  1372. + switch (GET_CODE (v_insn))
  1373. + {
  1374. + case CODE_LABEL:
  1375. + seen_before [INSN_UID (v_insn)] = *count_p;
  1376. + break;
  1377. + case INSN:
  1378. + /* The attr_length may be bigger than acctual insn length.
  1379. + So don't use it in the after_delayed_branch_sched phase. */
  1380. + *count_p += ( get_attr_length (insn) > 0
  1381. + && !after_delayed_branch_sched )
  1382. + ? get_attr_length (insn) : 4 ;
  1383. + if (detect_later)
  1384. + {
  1385. + /* inspect BD slot */
  1386. + if (NOP_INSN_P (PATTERN (v_insn)))
  1387. + return Reset;
  1388. + return Jump;
  1389. + }
  1390. + break;
  1391. + case JUMP_INSN:
  1392. + *jump_insn_p = v_insn;
  1393. + detect_later = 1;
  1394. + break;
  1395. + case CALL_INSN:
  1396. + return Reset;
  1397. + break;
  1398. + default:
  1399. + break;
  1400. + }
  1401. + }
  1402. +
  1403. + if (detect_later)
  1404. + /* Since there's no instruction in the delay slot, the assembler will
  1405. + insert a "nop" later. */
  1406. + return Reset;
  1407. +
  1408. + return Other;
  1409. +}
  1410. +
  1411. +/* XXX: Fix this. */
  1412. +
  1413. +static void
  1414. +r5900_lengthen_loops (first, after_delayed_branch_sched)
  1415. + rtx first;
  1416. + int after_delayed_branch_sched;
  1417. +{
  1418. + rtx insn;
  1419. + rtx this_jump_insn;
  1420. + const int hazardous_distance = 6;
  1421. + int n = 4;
  1422. + int max_uid = get_max_uid ();
  1423. + int *seen_before = alloca (sizeof seen_before[0] * max_uid);
  1424. + int in_sequence = 0;
  1425. + enum sequence_type result;
  1426. +
  1427. + /*bzero ((char *) seen_before, sizeof seen_before[0] * max_uid);*/
  1428. + memset((char *) seen_before, 0, sizeof seen_before[0] * max_uid);
  1429. +
  1430. + for (insn = first; insn; insn = NEXT_INSN (insn))
  1431. + {
  1432. + in_sequence = 0;
  1433. + switch (GET_CODE (insn))
  1434. + {
  1435. + case CODE_LABEL:
  1436. + seen_before [INSN_UID (insn)] = n;
  1437. + break;
  1438. +
  1439. + case INSN:
  1440. + if (GET_CODE (PATTERN (insn)) != SEQUENCE )
  1441. + {
  1442. + /* The attr_length may be bigger than acctual insn length.
  1443. + So don't use it in the after_delayed_branch_sched phase. */
  1444. + n += ( get_attr_length (insn) > 0
  1445. + && !after_delayed_branch_sched )
  1446. + ? get_attr_length (insn) : 4 ;
  1447. + break;
  1448. + }
  1449. + result = r5900_detect_sequence_type(insn, &n, &this_jump_insn,
  1450. + seen_before, after_delayed_branch_sched);
  1451. + switch(result)
  1452. + {
  1453. + case Reset:
  1454. + goto reset;
  1455. + case Jump:
  1456. + in_sequence=1;
  1457. + goto jump_insn;
  1458. + case Other:
  1459. + default:
  1460. + break;
  1461. + }
  1462. + break;
  1463. +
  1464. + case JUMP_INSN:
  1465. + this_jump_insn = insn;
  1466. + in_sequence=0;
  1467. + jump_insn:
  1468. + if (condjump_p (this_jump_insn))
  1469. + {
  1470. + rtx target = condjump_label (this_jump_insn);
  1471. +
  1472. + if (seen_before [INSN_UID (XEXP (target, 0))])
  1473. + {
  1474. + int distance
  1475. + = (n - seen_before [INSN_UID (XEXP (target, 0))]) >> 2;
  1476. +
  1477. + if (!in_sequence)
  1478. + {
  1479. + /* try to insert one nop before jump
  1480. + * if distance is in hazardous_distance */
  1481. +
  1482. + if ( distance <= hazardous_distance )
  1483. + {
  1484. + rtx prev_insn = PREV_INSN (this_jump_insn);
  1485. + while ( prev_insn && ( GET_CODE (prev_insn) != INSN ))
  1486. + prev_insn = PREV_INSN (prev_insn);
  1487. + if (prev_insn && ! NOP_INSN_P (PATTERN (prev_insn)))
  1488. + emit_insn_before (gen_nop (), this_jump_insn);
  1489. +
  1490. + }
  1491. + }
  1492. + else
  1493. + {
  1494. + if ( distance <= hazardous_distance )
  1495. + {
  1496. + for (; distance <= hazardous_distance; distance++)
  1497. + emit_insn_before (gen_nop(), insn);
  1498. + }
  1499. + }
  1500. + }
  1501. + }
  1502. +
  1503. + /* Falls through */
  1504. +
  1505. + case CALL_INSN:
  1506. + reset:
  1507. + /*bzero ((char *) seen_before, sizeof seen_before[0] * max_uid);*/
  1508. + memset((char *) seen_before, 0, sizeof seen_before[0] * max_uid);
  1509. + break;
  1510. +
  1511. + default:
  1512. + break;
  1513. + }
  1514. + }
  1515. +}
  1516. +
  1517. +/* Exported to toplev.c.
  1518. +
  1519. + Do a final pass over the function, just before rtl to asm conversion
  1520. + (after "delayed branch scheduling" and "shorten jump"). */
  1521. +
  1522. +void
  1523. +machine_dependent_reorg_final (first)
  1524. + rtx first;
  1525. +{
  1526. + if (TARGET_MIPS5900 && ! TARGET_NO_LENGTHEN_LOOP)
  1527. + r5900_lengthen_loops (first, 1);
  1528. +}
  1529. +
  1530. /* Return nonzero if X is a SIGN or ZERO extend operator. */
  1531. int
  1532. extend_operator (x, mode)
  1533. @@ -9978,6 +10524,8 @@
  1534. case '5':
  1535. if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
  1536. cpu = PROCESSOR_R5000;
  1537. + else if (!strcmp (p, "5900"))
  1538. + cpu = PROCESSOR_R5900;
  1539. else if (!strcmp (p, "5kc") || !strcmp (p, "5Kc") )
  1540. cpu = PROCESSOR_R5KC;
  1541. break;
  1542. @@ -10102,7 +10650,10 @@
  1543. int regno;
  1544. enum machine_mode mode;
  1545. {
  1546. - if (! FP_REG_P (regno))
  1547. + /* TODO: Add r5900 dual mode register support. */
  1548. + if (TARGET_MIPS5900 && GP_REG_P (regno) && mode == TImode)
  1549. + return 1;
  1550. + else if (! FP_REG_P (regno))
  1551. return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
  1552. else
  1553. return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
  1554. @@ -10268,3 +10819,345 @@
  1555. mips_asm_file_end (stream);
  1556. }
  1557. #endif /* TARGET_IRIX6 */
  1558. +
  1559. +static void
  1560. +r5900_sched_init ()
  1561. +{
  1562. +}
  1563. +
  1564. +static void
  1565. +mips_sched_init (dump, sched_verbose, veclen)
  1566. + FILE *dump ATTRIBUTE_UNUSED;
  1567. + int sched_verbose ATTRIBUTE_UNUSED;
  1568. + int veclen ATTRIBUTE_UNUSED;
  1569. +{
  1570. + if (TARGET_MIPS5900)
  1571. + r5900_sched_init ();
  1572. +}
  1573. +
  1574. +static void
  1575. +r5900_sched_reorder (dump, sched_verbose, ready, n_ready)
  1576. + FILE *dump;
  1577. + int sched_verbose;
  1578. + rtx *ready;
  1579. + int n_ready;
  1580. +{
  1581. + static int imuldivunit = -1;
  1582. +
  1583. + return;
  1584. + /* There is also no point in trying these tweaks after reload has
  1585. + completed. */
  1586. + if (reload_completed)
  1587. + return;
  1588. +
  1589. + /* If there are less than three insns on the queue, then there's nothing
  1590. + to do. */
  1591. + if (n_ready < 3)
  1592. + return;
  1593. +
  1594. + /* We need to know what value will be returned by function_units_used for
  1595. + the r5900's multiply/divide units. If we have not computed it yet,
  1596. + do so now. */
  1597. + if (imuldivunit == -1)
  1598. + {
  1599. + int i;
  1600. +
  1601. + for (i = 0; i < FUNCTION_UNITS_SIZE; i++)
  1602. + {
  1603. + if (!strcmp ("r5900imuldiv", function_units[i].name))
  1604. + {
  1605. + imuldivunit = i;
  1606. + break;
  1607. + }
  1608. + }
  1609. + if (imuldivunit == -1)
  1610. + return;
  1611. + }
  1612. +
  1613. + {
  1614. + int i;
  1615. +
  1616. + /* Loop through the instructions and try to pair up two instructions
  1617. + which use the imuldiv pipelines.
  1618. +
  1619. + We want such instructions to appear back to back in the RTL chain
  1620. + so that the register allocator will allocate a different HILO
  1621. + register for the two imuldiv instructions.
  1622. +
  1623. + Note the ready list is ordered backwards.
  1624. +
  1625. + If we do not find an idivmul insn which could issue this cycle, quit
  1626. + to save time. */
  1627. + for (i = n_ready - 1; i >= n_ready - 2; i--)
  1628. + {
  1629. + rtx insn = ready[i];
  1630. + enum rtx_code code;
  1631. +
  1632. + /* Ignore anything we do not understand. */
  1633. + if (GET_RTX_CLASS (GET_CODE (insn)) != 'i'
  1634. + || (code = GET_CODE (PATTERN (insn))) == USE
  1635. + || code == CLOBBER || code == ADDR_VEC)
  1636. + continue;
  1637. + else
  1638. + {
  1639. + /* We are looking for instructions that issue to the imuldiv
  1640. + pipelines. */
  1641. + if (function_units_used (insn) == imuldivunit)
  1642. + {
  1643. + int j;
  1644. +
  1645. + /* We have found one insn that uses the imuldiv pipeline, so
  1646. + now look for another imuldiv instruction. */
  1647. + for (j = i - 1; j >= 0; j--)
  1648. + {
  1649. + rtx temp = ready[j];
  1650. +
  1651. + /* Ignore anything we do not understand. */
  1652. + if (GET_RTX_CLASS (GET_CODE (temp)) != 'i'
  1653. + || (code = GET_CODE (PATTERN (temp))) == USE
  1654. + || code == CLOBBER || code == ADDR_VEC)
  1655. + continue;
  1656. +
  1657. + /* Again, we are looking for an imuldiv insn. */
  1658. + if (function_units_used (temp) == imuldivunit)
  1659. + {
  1660. +
  1661. + /* Make the idivmul insns consecutive if they were
  1662. + not already consecutive. */
  1663. + if (i - j != 1)
  1664. + {
  1665. + rtx temp = ready[j];
  1666. + /*bcopy (&ready[j+1], &ready[j],
  1667. + (i - j - 1) * sizeof (rtx *));*/
  1668. + memcpy(&ready[j], &ready[j+1], (i - j - 1) * sizeof (rtx *));
  1669. + ready[i - 1] = temp;
  1670. + }
  1671. +
  1672. + /* Now the imuldiv insns are consecutive. We can
  1673. + still lose if they issue at different clocks, so
  1674. + move them as a pair to the head of ready list.
  1675. +
  1676. + Note I must either be the head of the queue or
  1677. + the second insn in the queue. */
  1678. + if (i != n_ready - 1)
  1679. + {
  1680. + rtx temp1, temp2;
  1681. +
  1682. + /* Rotate the first three elements in the
  1683. + ready queue. */
  1684. + temp1 = ready[n_ready - 1];
  1685. + temp2 = ready[n_ready - 2];
  1686. + ready[n_ready - 2] = ready[n_ready - 3];
  1687. + ready[n_ready - 3] = temp1;
  1688. + ready[n_ready - 1] = temp2;
  1689. + }
  1690. + return;
  1691. + }
  1692. + }
  1693. + }
  1694. + }
  1695. + }
  1696. + }
  1697. +}
  1698. +
  1699. +/* Reorder the ready list as needed to improve performance. */
  1700. +
  1701. +static int
  1702. +mips_sched_reorder (dump, sched_verbose, ready, n_readyp, clock_var)
  1703. + FILE *dump ATTRIBUTE_UNUSED;
  1704. + int sched_verbose ATTRIBUTE_UNUSED;
  1705. + rtx *ready;
  1706. + int *n_readyp;
  1707. + int clock_var ATTRIBUTE_UNUSED;
  1708. +{
  1709. + if (TARGET_MIPS5900)
  1710. + r5900_sched_reorder (dump, sched_verbose, ready, *n_readyp);
  1711. + return ISSUE_RATE;
  1712. +}
  1713. +
  1714. +/* R5900 built-ins support. This is largely based off of the ix86 SSE/MMX
  1715. + and rs6000 Altivec implementations. */
  1716. +
  1717. +#define def_builtin(MASK, NAME, TYPE, CODE) \
  1718. +do { \
  1719. + if ((MASK) & target_flags) \
  1720. + builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL); \
  1721. +} while (0)
  1722. +
  1723. +struct builtin_description
  1724. +{
  1725. + const unsigned int mask;
  1726. + const enum insn_code icode;
  1727. + const char *const name;
  1728. + const enum r5900_builtins code;
  1729. +};
  1730. +
  1731. +/* Builtins that take 2 arguments. */
  1732. +static struct builtin_description bdesc_2arg[] =
  1733. +{
  1734. + { MASK_MMI, CODE_FOR_addv16qi3, "__builtin_mmi_paddb", MMI_BUILTIN_PADDB },
  1735. + { MASK_MMI, CODE_FOR_addv8hi3, "__builtin_mmi_paddh", MMI_BUILTIN_PADDH },
  1736. + { MASK_MMI, CODE_FOR_addv4si3, "__builtin_mmi_paddw", MMI_BUILTIN_PADDW },
  1737. + { MASK_MMI, CODE_FOR_ssaddv16qi3, "__builtin_mmi_paddsb", MMI_BUILTIN_PADDSB },
  1738. + { MASK_MMI, CODE_FOR_ssaddv8hi3, "__builtin_mmi_paddsh", MMI_BUILTIN_PADDSW },
  1739. + { MASK_MMI, CODE_FOR_ssaddv4si3, "__builtin_mmi_paddsw", MMI_BUILTIN_PADDSH },
  1740. + { MASK_MMI, CODE_FOR_usaddv16qi3, "__builtin_mmi_paddub", MMI_BUILTIN_PADDUB },
  1741. + { MASK_MMI, CODE_FOR_usaddv8hi3, "__builtin_mmi_padduh", MMI_BUILTIN_PADDUW },
  1742. + { MASK_MMI, CODE_FOR_usaddv4si3, "__builtin_mmi_padduw", MMI_BUILTIN_PADDUH },
  1743. +
  1744. + { MASK_MMI, CODE_FOR_subv16qi3, "__builtin_mmi_psubb", MMI_BUILTIN_PSUBB },
  1745. + { MASK_MMI, CODE_FOR_subv8hi3, "__builtin_mmi_psubh", MMI_BUILTIN_PSUBH },
  1746. + { MASK_MMI, CODE_FOR_subv4si3, "__builtin_mmi_psubw", MMI_BUILTIN_PSUBW },
  1747. + { MASK_MMI, CODE_FOR_sssubv16qi3, "__builtin_mmi_psubsb", MMI_BUILTIN_PSUBSB },
  1748. + { MASK_MMI, CODE_FOR_sssubv8hi3, "__builtin_mmi_psubsh", MMI_BUILTIN_PSUBSW },
  1749. + { MASK_MMI, CODE_FOR_sssubv4si3, "__builtin_mmi_psubsw", MMI_BUILTIN_PSUBSH },
  1750. + { MASK_MMI, CODE_FOR_ussubv16qi3, "__builtin_mmi_psubub", MMI_BUILTIN_PSUBUB },
  1751. + { MASK_MMI, CODE_FOR_ussubv8hi3, "__builtin_mmi_psubuh", MMI_BUILTIN_PSUBUW },
  1752. + { MASK_MMI, CODE_FOR_ussubv4si3, "__builtin_mmi_psubuw", MMI_BUILTIN_PSUBUH },
  1753. +
  1754. +};
  1755. +
  1756. +/* Expand all r5900-specific builtins. This is only called if TARGET_MMI or
  1757. + TARGET_VUMM are true. */
  1758. +static void
  1759. +r5900_init_builtins()
  1760. +{
  1761. + struct builtin_description *d;
  1762. + size_t i;
  1763. + tree endlink = void_list_node;
  1764. +
  1765. + /* Normal vector binops. */
  1766. + tree v16qi_ftype_v16qi_v16qi
  1767. + = build_function_type (V16QI_type_node,
  1768. + tree_cons (NULL_TREE, V16QI_type_node,
  1769. + tree_cons (NULL_TREE, V16QI_type_node,
  1770. + endlink)));
  1771. +
  1772. + tree v8hi_ftype_v8hi_v8hi
  1773. + = build_function_type (V8HI_type_node,
  1774. + tree_cons (NULL_TREE, V8HI_type_node,
  1775. + tree_cons (NULL_TREE, V8HI_type_node,
  1776. + endlink)));
  1777. +
  1778. + tree v4si_ftype_v4si_v4si
  1779. + = build_function_type (V4SI_type_node,
  1780. + tree_cons (NULL_TREE, V4SI_type_node,
  1781. + tree_cons (NULL_TREE, V4SI_type_node,
  1782. + endlink)));
  1783. +
  1784. + tree ti_ftype_ti_ti
  1785. + = build_function_type (intTI_type_node,
  1786. + tree_cons (NULL_TREE, intTI_type_node,
  1787. + tree_cons (NULL_TREE, intTI_type_node,
  1788. + endlink)));
  1789. +
  1790. + /* Add all builtins that are simple binary operations. */
  1791. + for (i = 0, d = bdesc_2arg; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
  1792. + {
  1793. + enum machine_mode mode;
  1794. + tree type;
  1795. +
  1796. + if (d->name == 0)
  1797. + continue;
  1798. + mode = insn_data[d->icode].operand[1].mode;
  1799. +
  1800. + switch (mode)
  1801. + {
  1802. + case V16QImode:
  1803. + type = v16qi_ftype_v16qi_v16qi;
  1804. + break;
  1805. + case V8HImode:
  1806. + type = v8hi_ftype_v8hi_v8hi;
  1807. + case V4SImode:
  1808. + type = v4si_ftype_v4si_v4si;
  1809. + case TImode:
  1810. + type = ti_ftype_ti_ti;
  1811. + break;
  1812. +
  1813. + default:
  1814. + abort ();
  1815. + }
  1816. +
  1817. + def_builtin (d->mask, d->name, type, d->code);
  1818. + }
  1819. +}
  1820. +
  1821. +static rtx
  1822. +r5900_expand_binop_builtin (icode, arglist, target)
  1823. + enum insn_code icode;
  1824. + tree arglist;
  1825. + rtx target;
  1826. +{
  1827. + rtx pat;
  1828. + tree arg0 = TREE_VALUE (arglist);
  1829. + tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
  1830. + rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
  1831. + rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
  1832. + enum machine_mode tmode = insn_data[icode].operand[0].mode;
  1833. + enum machine_mode mode0 = insn_data[icode].operand[1].mode;
  1834. + enum machine_mode mode1 = insn_data[icode].operand[2].mode;
  1835. +
  1836. + if (! target
  1837. + || GET_MODE (target) != tmode
  1838. + || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
  1839. + target = gen_reg_rtx (tmode);
  1840. +
  1841. + /* In case the insn wants input operands in modes different fro
  1842. + the result, abort. */
  1843. + if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
  1844. + abort ();
  1845. +
  1846. + if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
  1847. + op0 = copy_to_mode_reg (mode0, op0);
  1848. + if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
  1849. + op1 = copy_to_mode_reg (mode1, op1);
  1850. +
  1851. + pat = GEN_FCN (icode) (target, op0, op1);
  1852. + if (! pat)
  1853. + return 0;
  1854. + emit_insn (pat);
  1855. + return target;
  1856. +}
  1857. +
  1858. +static rtx
  1859. +r5900_expand_builtin (exp, target)
  1860. + tree exp;
  1861. + rtx target;
  1862. +{
  1863. + struct builtin_description *d;
  1864. + size_t i;
  1865. + enum insn_code icode;
  1866. + tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
  1867. + tree arglist = TREE_OPERAND (exp, 1);
  1868. + tree arg0, arg1, arg2, arg3;
  1869. + rtx op0, op1, op2, pat;
  1870. + enum machine_mode tmode, mode0, mode1, mode2;
  1871. + unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
  1872. +
  1873. + for (i = 0, d = bdesc_2arg; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
  1874. + if (d->code == fcode)
  1875. + return r5900_expand_binop_builtin (d->icode, arglist, target);
  1876. +
  1877. + return 0;
  1878. +}
  1879. +
  1880. +static rtx
  1881. +mips_expand_builtin (exp, target, subtarget, mode, ignore)
  1882. + tree exp;
  1883. + rtx target;
  1884. + rtx subtarget ATTRIBUTE_UNUSED;
  1885. + enum machine_mode mode ATTRIBUTE_UNUSED;
  1886. + int ignore ATTRIBUTE_UNUSED;
  1887. +{
  1888. + if (TARGET_MIPS5900)
  1889. + return r5900_expand_builtin (exp, target);
  1890. +
  1891. + abort ();
  1892. +}
  1893. +
  1894. +static void
  1895. +mips_init_builtins ()
  1896. +{
  1897. + if (TARGET_MIPS5900)
  1898. + r5900_init_builtins ();
  1899. +}
  1900. diff -burN orig.gcc-3.2.3/gcc/config/mips/mips.h gcc-3.2.3/gcc/config/mips/mips.h
  1901. --- orig.gcc-3.2.3/gcc/config/mips/mips.h 2002-04-26 18:32:14.000000000 -0300
  1902. +++ gcc-3.2.3/gcc/config/mips/mips.h 2015-08-10 16:11:20 +0300
  1903. @@ -48,6 +48,7 @@
  1904. DELAY_NONE, /* no delay slot */
  1905. DELAY_LOAD, /* load from memory delay */
  1906. DELAY_HILO, /* move from/to hi/lo registers */
  1907. + DELAY_HILO1, /* move from/to hi1/lo1 registers */
  1908. DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
  1909. };
  1910.  
  1911. @@ -67,6 +68,7 @@
  1912. PROCESSOR_R4600,
  1913. PROCESSOR_R4650,
  1914. PROCESSOR_R5000,
  1915. + PROCESSOR_R5900,
  1916. PROCESSOR_R8000,
  1917. PROCESSOR_R4KC,
  1918. PROCESSOR_R5KC,
  1919. @@ -146,6 +148,7 @@
  1920. extern int mips16; /* whether generating mips16 code */
  1921. extern int mips16_hard_float; /* mips16 without -msoft-float */
  1922. extern int mips_entry; /* generate entry/exit for mips16 */
  1923. +extern int mips_alignment; /* max alignment bits */
  1924. extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
  1925. extern const char *mips_arch_string; /* for -march=<xxx> */
  1926. extern const char *mips_tune_string; /* for -mtune=<xxx> */
  1927. @@ -155,6 +158,11 @@
  1928. extern const char *mips_no_mips16_string;/* for -mno-mips16 */
  1929. extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
  1930. extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
  1931. +extern const char *mips_align_all_string;/* for -malign-all= */
  1932. +extern const char * mips_align128_string;/* for -malign128 */
  1933. +extern const char * mips_no_align128_string;/* for -mno-align128 */
  1934. +extern const char * mips_use_128_string; /* for -muse-128 */
  1935. +extern int mips_use_128; /* the boolean for -muse-128 */
  1936. extern int mips_split_addresses; /* perform high/lo_sum support */
  1937. extern int dslots_load_total; /* total # load related delay slots */
  1938. extern int dslots_load_filled; /* # filled load delay slots */
  1939. @@ -175,6 +183,8 @@
  1940. extern void sdata_section PARAMS ((void));
  1941. extern void sbss_section PARAMS ((void));
  1942.  
  1943. +extern int mips_align_all;
  1944. +
  1945. /* Stubs for half-pic support if not OSF/1 reference platform. */
  1946.  
  1947. #ifndef HALF_PIC_P
  1948. @@ -232,6 +242,10 @@
  1949. consts in rodata */
  1950. #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
  1951. multiply-add operations. */
  1952. +#define MASK_MMI 0x02000000 /* r5900 MultiMedia Instructions (MMI) */
  1953. +#define MASK_VUMM 0x04000000 /* r5900 VU0 macro mode (COP2) */
  1954. +#define MASK_NO_LENGTHEN_LOOP \
  1955. + 0x08000000 /* Disable r5900 loop bug workaround */
  1956.  
  1957. /* Debug switches, not documented */
  1958. #define MASK_DEBUG 0 /* unused */
  1959. @@ -327,6 +341,16 @@
  1960. #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
  1961. #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
  1962.  
  1963. + /* enable r5900 multimedia
  1964. + instructions. */
  1965. +#define TARGET_MMI (target_flags & MASK_MMI)
  1966. +
  1967. + /* enable r5900 macro mode for VU0 */
  1968. +#define TARGET_VUMM (target_flags & MASK_VUMM)
  1969. +
  1970. + /* disable r5900 loop bug workaround */
  1971. +#define TARGET_NO_LENGTHEN_LOOP (target_flags & MASK_NO_LENGTHEN_LOOP)
  1972. +
  1973. /* This is true if we must enable the assembly language file switching
  1974. code. */
  1975.  
  1976. @@ -346,6 +370,7 @@
  1977. #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
  1978. #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
  1979. #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
  1980. +#define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
  1981. #define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
  1982. #define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
  1983.  
  1984. @@ -354,6 +379,7 @@
  1985. #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
  1986. #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
  1987. #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
  1988. +#define TUNE_MIPS5900 (mips_tune == PROCESSOR_R5900)
  1989. #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
  1990.  
  1991. /* Macro to define tables used to set the flags.
  1992. @@ -464,6 +490,18 @@
  1993. N_("Optimize for 3900")}, \
  1994. {"4650", 0, \
  1995. N_("Optimize for 4650")}, \
  1996. + {"5900", 0, \
  1997. + N_("Optimize for 5900")}, \
  1998. + {"mmi", MASK_MMI, \
  1999. + N_("Use r5900 multimedia instructions")}, \
  2000. + {"no-mmi", -MASK_MMI, \
  2001. + N_("Don't use r5900 multimedia instructions")}, \
  2002. + {"vumm", MASK_VUMM, \
  2003. + N_("Use r5900 VU0 macro mode instructions")}, \
  2004. + {"no-vumm", -MASK_VUMM, \
  2005. + N_("Don't use r5900 VU0 macro mode instructions")}, \
  2006. + {"no-lengthen-loop", MASK_NO_LENGTHEN_LOOP, \
  2007. + N_("Don't workaround r5900 short loop bug")}, \
  2008. {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
  2009. N_("Trap on integer divide by zero")}, \
  2010. {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
  2011. @@ -472,6 +510,8 @@
  2012. N_("Trap on integer divide overflow")}, \
  2013. {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
  2014. N_("Don't trap on integer divide overflow")}, \
  2015. + {"iop", 0, \
  2016. + N_("Output IOP's IRX file")}, \
  2017. {"debug", MASK_DEBUG, \
  2018. NULL}, \
  2019. {"debuga", MASK_DEBUG_A, \
  2020. @@ -604,6 +644,8 @@
  2021. N_("Don't call any cache flush functions")}, \
  2022. { "flush-func=", &mips_cache_flush_func, \
  2023. N_("Specify cache flush function")}, \
  2024. + { "align-all=", &mips_align_all_string, \
  2025. + N_("Force lower alignment")}, \
  2026. }
  2027.  
  2028. /* This is meant to be redefined in the host dependent files. */
  2029. @@ -613,6 +655,7 @@
  2030.  
  2031. /* Generate three-operand multiply instructions for SImode. */
  2032. #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
  2033. + || TARGET_MIPS5900 \
  2034. || mips_isa == 32 \
  2035. || mips_isa == 64) \
  2036. && !TARGET_MIPS16)
  2037. @@ -644,7 +687,7 @@
  2038. || mips_isa == 64)
  2039.  
  2040. /* ISA has just the integer condition move instructions (movn,movz) */
  2041. -#define ISA_HAS_INT_CONDMOVE 0
  2042. +#define ISA_HAS_INT_CONDMOVE (TARGET_MIPS5900)
  2043.  
  2044.  
  2045.  
  2046. @@ -847,7 +890,7 @@
  2047. /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
  2048. assembler. */
  2049.  
  2050. -#define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64} %(abi_gas_asm_spec) %{mabi=32:%{!mips*:-mips1}}"
  2051. +#define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{m5900} %{v} %{mgp32} %{mgp64} %(abi_gas_asm_spec) %{mabi=32:%{!mips*:-mips1}}"
  2052.  
  2053.  
  2054. extern int mips_abi;
  2055. @@ -964,7 +1007,7 @@
  2056. #ifndef LINK_SPEC
  2057. #define LINK_SPEC "\
  2058. %(endian_spec) \
  2059. -%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
  2060. +%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} %{miop:-mmipsirx} \
  2061. %{bestGnum} %{shared} %{non_shared}"
  2062. #endif /* LINK_SPEC defined */
  2063.  
  2064. @@ -984,7 +1027,9 @@
  2065. %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
  2066. %n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
  2067. %{m4650:-march=r4650 -mmad -msingle-float \
  2068. -%n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
  2069. +%n`-m4650' is deprecated. Use `-march=r4650' instead.\n} \
  2070. +%{m5900:-march=r5900 -mips3 -mgp64 -mfp32 -mlong64 -mmmi -msingle-float \
  2071. +%n`-m5900' is deprecated. Use `-march=r5900' instead.\n}}"
  2072. #endif
  2073.  
  2074. /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
  2075. @@ -1003,6 +1048,7 @@
  2076. %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
  2077. %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
  2078. %{mint64|mlong64|mlong32:-mexplicit-type-size }\
  2079. +%{miop:-march=r3000 -mfp32 -mgp32 -fno-builtin} \
  2080. %{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \
  2081. %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
  2082. %{pic-none: -mno-half-pic} \
  2083. @@ -1661,7 +1707,7 @@
  2084. #define STRUCTURE_SIZE_BOUNDARY 8
  2085.  
  2086. /* There is no point aligning anything to a rounder boundary than this. */
  2087. -#define BIGGEST_ALIGNMENT 64
  2088. +#define BIGGEST_ALIGNMENT 128
  2089.  
  2090. /* Set this nonzero if move instructions will actually fail to work
  2091. when given unaligned data. */
  2092. @@ -1796,20 +1842,20 @@
  2093. address reg ($31) was stored. This is needed for C++ exception
  2094. handling. */
  2095.  
  2096. -#define FIRST_PSEUDO_REGISTER 76
  2097. +#define FIRST_PSEUDO_REGISTER 79
  2098.  
  2099. /* 1 for registers that have pervasive standard uses
  2100. and are not available for the register allocator.
  2101.  
  2102. On the MIPS, see conventions, page D-2 */
  2103. -
  2104. #define FIXED_REGISTERS \
  2105. { \
  2106. 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
  2107. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
  2108. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
  2109. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
  2110. - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
  2111. + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
  2112. + 0, 0, 0 \
  2113. }
  2114.  
  2115.  
  2116. @@ -1826,7 +1872,8 @@
  2117. 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
  2118. 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
  2119. 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
  2120. - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
  2121. + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
  2122. + 1, 1, 1 \
  2123. }
  2124.  
  2125. /* Like `CALL_USED_REGISTERS' but used to overcome a historical
  2126. @@ -1846,7 +1893,8 @@
  2127. 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
  2128. 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
  2129. /* Others. */ \
  2130. - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
  2131. + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
  2132. + 1, 1, 1 \
  2133. }
  2134.  
  2135. /* Internal macros to classify a register number as to whether it's a
  2136. @@ -1867,6 +1915,10 @@
  2137. #define MD_REG_LAST 66
  2138. #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
  2139.  
  2140. +#define MD1_REG_FIRST 76
  2141. +#define MD1_REG_LAST 78
  2142. +#define MD1_REG_NUM (MD1_REG_LAST - MD1_REG_FIRST + 1)
  2143. +
  2144. #define ST_REG_FIRST 67
  2145. #define ST_REG_LAST 74
  2146. #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
  2147. @@ -1877,6 +1929,9 @@
  2148. #define HI_REGNUM (MD_REG_FIRST + 0)
  2149. #define LO_REGNUM (MD_REG_FIRST + 1)
  2150. #define HILO_REGNUM (MD_REG_FIRST + 2)
  2151. +#define HI1_REGNUM (MD1_REG_FIRST + 0)
  2152. +#define LO1_REGNUM (MD1_REG_FIRST + 1)
  2153. +#define HILO1_REGNUM (MD1_REG_FIRST + 2)
  2154.  
  2155. /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
  2156. mips_isa >= 4, it should not be used, and an arbitrary ST_REG
  2157. @@ -1891,6 +1946,8 @@
  2158. ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
  2159. #define MD_REG_P(REGNO) \
  2160. ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
  2161. +#define MD1_REG_P(REGNO) \
  2162. + ((unsigned int) ((int) (REGNO) - MD1_REG_FIRST) < MD1_REG_NUM)
  2163. #define ST_REG_P(REGNO) \
  2164. ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
  2165.  
  2166. @@ -2057,6 +2114,20 @@
  2167. LO_AND_GR_REGS,
  2168. HILO_AND_GR_REGS,
  2169. HI_AND_FP_REGS,
  2170. + HI1_REG, /* hi1 register */
  2171. + LO1_REG, /* lo1 register */
  2172. + HILO1_REG, /* hilo1 register pair for 64 bit mode mult */
  2173. + MD1_REGS, /* multiply/divide registers (hi/lo) */
  2174. + HI1_AND_GR_REGS, /* union classes */
  2175. + LO1_AND_GR_REGS,
  2176. + HILO1_AND_GR_REGS,
  2177. + HI01_REG, /* hi01 register */
  2178. + LO01_REG, /* lo01 register */
  2179. + HILO01_REG, /* hilo1 register pair for 64 bit mode mult */
  2180. + MD01_REGS, /* multiply/divide registers (hi1/lo1) */
  2181. + HI01_AND_GR_REGS, /* union classes */
  2182. + LO01_AND_GR_REGS,
  2183. + HILO01_AND_GR_REGS,
  2184. ST_REGS, /* status registers (fp status) */
  2185. ALL_REGS, /* all registers */
  2186. LIM_REG_CLASSES /* max value + 1 */
  2187. @@ -2087,6 +2158,20 @@
  2188. "LO_AND_GR_REGS", \
  2189. "HILO_AND_GR_REGS", \
  2190. "HI_AND_FP_REGS", \
  2191. + "HI1_REG", \
  2192. + "LO1_REG", \
  2193. + "HILO1_REG", \
  2194. + "MD1_REGS", \
  2195. + "HI1_AND_GR_REGS", \
  2196. + "LO1_AND_GR_REGS", \
  2197. + "HILO1_AND_GR_REGS", \
  2198. + "HI01_REG", \
  2199. + "LO01_REG", \
  2200. + "HILO01_REG", \
  2201. + "MD01_REGS", \
  2202. + "HI01_AND_GR_REGS", \
  2203. + "LO01_AND_GR_REGS", \
  2204. + "HILO01_AND_GR_REGS", \
  2205. "ST_REGS", \
  2206. "ALL_REGS" \
  2207. }
  2208. @@ -2105,7 +2190,7 @@
  2209. #define REG_CLASS_CONTENTS \
  2210. { \
  2211. { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
  2212. - { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
  2213. + { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */ \
  2214. { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
  2215. { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
  2216. { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
  2217. @@ -2119,8 +2204,24 @@
  2218. { 0xffffffff, 0x00000000, 0x00000002 }, \
  2219. { 0xffffffff, 0x00000000, 0x00000004 }, \
  2220. { 0x00000000, 0xffffffff, 0x00000001 }, \
  2221. + /* Start of r5900 extra registers. */ \
  2222. + { 0x00000000, 0x00000000, 0x00001000 }, /* hi1 register */ \
  2223. + { 0x00000000, 0x00000000, 0x00002000 }, /* lo1 register */ \
  2224. + { 0x00000000, 0x00000000, 0x00004000 }, /* hilo1 register */ \
  2225. + { 0x00000000, 0x00000000, 0x00003000 }, /* mul1/div1 registers */ \
  2226. + { 0xffffffff, 0x00000000, 0x00001000 }, /* union classes */ \
  2227. + { 0xffffffff, 0x00000000, 0x00002000 }, \
  2228. + { 0xffffffff, 0x00000000, 0x00004000 }, \
  2229. + { 0x00000000, 0x00000000, 0x00001001 }, /* hi01 registers */ \
  2230. + { 0x00000000, 0x00000000, 0x00002002 }, /* lo01 registers */ \
  2231. + { 0x00000000, 0x00000000, 0x00004004 }, /* hilo01 registers */ \
  2232. + { 0x00000000, 0x00000000, 0x00003003 }, /* mul01/div01 registers */ \
  2233. + { 0xffffffff, 0x00000000, 0x00001001 }, /* union classes */ \
  2234. + { 0xffffffff, 0x00000000, 0x00002002 }, \
  2235. + { 0xffffffff, 0x00000000, 0x00004004 }, \
  2236. + /* End of r5900 extra registers. */ \
  2237. { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
  2238. - { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
  2239. + { 0xffffffff, 0xffffffff, 0x000078ff } /* all registers */ \
  2240. }
  2241.  
  2242.  
  2243. @@ -2169,7 +2270,8 @@
  2244. 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
  2245. 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
  2246. 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
  2247. - 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
  2248. + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, \
  2249. + 76, 77, 78 \
  2250. }
  2251.  
  2252. /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
  2253. @@ -2197,7 +2299,11 @@
  2254. 'x' Multiply/divide registers
  2255. 'a' HILO_REG
  2256. 'z' FP Status register
  2257. - 'b' All registers */
  2258. + 'b' All registers
  2259. + 'u' Hi1 register
  2260. + 'v' Lo1 register
  2261. + 'w' Multiply/divide1 registers
  2262. + 'q' HILO1_REG */
  2263.  
  2264. extern enum reg_class mips_char_to_class[256];
  2265.  
  2266. @@ -2357,7 +2463,7 @@
  2267. #define CLASS_CANNOT_CHANGE_MODE \
  2268. (TARGET_BIG_ENDIAN \
  2269. ? (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS) \
  2270. - : (TARGET_FLOAT64 && ! TARGET_64BIT ? HI_AND_FP_REGS : HI_REG))
  2271. + : (TARGET_FLOAT64 && ! TARGET_64BIT ? HI_AND_FP_REGS : HI01_REG))
  2272.  
  2273. /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
  2274.  
  2275. @@ -3470,8 +3576,9 @@
  2276.  
  2277. /* Max number of bytes we can move from memory to memory
  2278. in one reasonably fast instruction. */
  2279. -#define MOVE_MAX (TARGET_64BIT ? 8 : 4)
  2280. -#define MAX_MOVE_MAX 8
  2281. +/* We can do 16 bytes using the r5900's MMI */
  2282. +#define MOVE_MAX (TARGET_MIPS5900 ? (mips_use_128 ? 16 : 8) : (TARGET_64BIT ? 8 : 4))
  2283. +#define MAX_MOVE_MAX (mips_use_128 ? 16 : 8)
  2284.  
  2285. /* Define this macro as a C expression which is nonzero if
  2286. accessing less than a word of memory (i.e. a `char' or a
  2287. @@ -3764,6 +3871,8 @@
  2288. return COSTS_N_INSNS (17); \
  2289. else if (TUNE_MIPS5000) \
  2290. return COSTS_N_INSNS (5); \
  2291. + else if (TUNE_MIPS5900) \
  2292. + return (xmode == SImode ? COSTS_N_INSNS (3) : COSTS_N_INSNS (30));\
  2293. else \
  2294. return COSTS_N_INSNS (10); \
  2295. } \
  2296. @@ -3805,6 +3914,8 @@
  2297. return COSTS_N_INSNS (38); \
  2298. else if (TUNE_MIPS5000) \
  2299. return COSTS_N_INSNS (36); \
  2300. + else if (TUNE_MIPS5900) \
  2301. + return COSTS_N_INSNS (30); \
  2302. else \
  2303. return COSTS_N_INSNS (69); \
  2304. \
  2305. @@ -3910,10 +4021,14 @@
  2306. : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
  2307. : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
  2308. : (((FROM) == HI_REG || (FROM) == LO_REG \
  2309. - || (FROM) == MD_REGS || (FROM) == HILO_REG) \
  2310. + || (FROM) == MD_REGS || (FROM) == HILO_REG \
  2311. + || (FROM) == HI1_REG || (FROM) == LO1_REG \
  2312. + || (FROM) == MD1_REGS || (FROM) == HILO1_REG) \
  2313. && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
  2314. : (((TO) == HI_REG || (TO) == LO_REG \
  2315. - || (TO) == MD_REGS || (TO) == HILO_REG) \
  2316. + || (TO) == MD_REGS || (TO) == HILO_REG \
  2317. + || (TO) == HI1_REG || (TO) == LO1_REG \
  2318. + || (TO) == MD1_REGS || (TO) == HILO1_REG) \
  2319. && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
  2320. : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
  2321. : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
  2322. @@ -3947,6 +4062,10 @@
  2323. #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  2324. ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
  2325.  
  2326. +/* The r5900 is a dual issue processor. */
  2327. +#undef ISSUE_RATE
  2328. +#define ISSUE_RATE ((TARGET_MIPS5900) ? 2 : 1)
  2329. +
  2331. /* Optionally define this if you have added predicates to
  2332. `MACHINE.c'. This macro is called within an initializer of an
  2333. @@ -3992,6 +4111,8 @@
  2334. {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
  2335. SYMBOL_REF, LABEL_REF, SUBREG, REG, \
  2336. MEM, SIGN_EXTEND }}, \
  2337. + {"movti_operand", { REG, MEM, CONST_INT, CONST_DOUBLE, \
  2338. + SUBREG }}, \
  2339. {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
  2340. {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
  2341. SIGN_EXTEND }}, \
  2342. @@ -4147,6 +4268,9 @@
  2343. &mips_reg_names[73][0], \
  2344. &mips_reg_names[74][0], \
  2345. &mips_reg_names[75][0], \
  2346. + &mips_reg_names[76][0], \
  2347. + &mips_reg_names[77][0], \
  2348. + &mips_reg_names[78][0], \
  2349. }
  2350.  
  2351. /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
  2352. @@ -4162,7 +4286,8 @@
  2353. "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
  2354. "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
  2355. "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
  2356. - "$fcc5","$fcc6","$fcc7","$rap" \
  2357. + "$fcc5","$fcc6","$fcc7","$rap", \
  2358. + "hi1", "lo1", "accum1" \
  2359. }
  2360.  
  2361. /* If defined, a C initializer for an array of structures
  2362. @@ -4415,6 +4540,7 @@
  2363. } while (0)
  2364.  
  2365. /* This says how to define a global common symbol. */
  2366. +/* ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); */
  2367.  
  2368. #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
  2369. do { \
  2370. @@ -4433,9 +4559,10 @@
  2371. mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
  2372. (SIZE)); \
  2373. } \
  2374. - else \
  2375. - mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
  2376. - (SIZE)); \
  2377. + else { \
  2378. + mips_declare_object_align (STREAM, NAME, "\n\t.comm\t", ",%u,%u\n", \
  2379. + (SIZE),(ALIGN / BITS_PER_UNIT)); \
  2380. + } \
  2381. } while (0)
  2382.  
  2383.  
  2384. @@ -4547,7 +4674,7 @@
  2385. to a multiple of 2**LOG bytes. */
  2386.  
  2387. #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
  2388. - fprintf (STREAM, "\t.align\t%d\n", (LOG))
  2389. + fprintf (STREAM, "\t.align\t%d\n", (LOG) > mips_align_all ? (LOG) : mips_align_all)
  2390.  
  2391. /* This is how to output an assembler line to advance the location
  2392. counter by SIZE bytes. */
  2393. @@ -4721,6 +4848,15 @@
  2394. PC relative loads that are out of range. */
  2395. #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
  2396.  
  2397. +/* This is used to lengthen short loops on the r5900. */
  2398. +#define MACHINE_DEPENDENT_REORG_FINAL(X) \
  2399. +do \
  2400. + { \
  2401. + if (TARGET_MIPS5900 && ! TARGET_NO_LENGTHEN_LOOP) \
  2402. + machine_dependent_reorg_final (X); \
  2403. + } \
  2404. +while (0)
  2405. +
  2406. /* We need to use a special set of functions to handle hard floating
  2407. point code in mips16 mode. */
  2408.  
  2409. @@ -4793,3 +4929,44 @@
  2410. } \
  2411. } \
  2412. while (0)
  2413. +
  2414. +/* r5900 vector mode & built-in support. */
  2415. +
  2416. +#define VALID_MMI_REG_MODE(MODE) \
  2417. + ((MODE) == TImode || (MODE) == V16QImode || (MODE) == V8HImode \
  2418. + || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V2DImode)
  2419. +
  2420. +#define VALID_VUMM_REG_MODE(MODE) \
  2421. + ((MODE) == TImode || (MODE) == V4SFmode)
  2422. +
  2423. +#define VECTOR_MODE_SUPPORTED_P(MODE) \
  2424. + ((VALID_MMI_REG_MODE (MODE) && TARGET_MMI) \
  2425. + || (VALID_VUMM_REG_MODE (MODE) && TARGET_VUMM) ? 1 : 0)
  2426. +
  2427. +enum r5900_builtins
  2428. +{
  2429. + /* MMI built-ins */
  2430. + MMI_BUILTIN_PADDB,
  2431. + MMI_BUILTIN_PADDH,
  2432. + MMI_BUILTIN_PADDW,
  2433. + MMI_BUILTIN_PADDSB,
  2434. + MMI_BUILTIN_PADDSH,
  2435. + MMI_BUILTIN_PADDSW,
  2436. + MMI_BUILTIN_PADDUB,
  2437. + MMI_BUILTIN_PADDUH,
  2438. + MMI_BUILTIN_PADDUW,
  2439. +
  2440. + MMI_BUILTIN_PSUBB,
  2441. + MMI_BUILTIN_PSUBH,
  2442. + MMI_BUILTIN_PSUBW,
  2443. + MMI_BUILTIN_PSUBSB,
  2444. + MMI_BUILTIN_PSUBSH,
  2445. + MMI_BUILTIN_PSUBSW,
  2446. + MMI_BUILTIN_PSUBUB,
  2447. + MMI_BUILTIN_PSUBUH,
  2448. + MMI_BUILTIN_PSUBUW,
  2449. +
  2450. + /* VU macro mode built-ins */
  2451. +
  2452. + R5900_BUILTIN_MAX
  2453. +};
  2454. diff -burN orig.gcc-3.2.3/gcc/config/mips/mips.md gcc-3.2.3/gcc/config/mips/mips.md
  2455. --- orig.gcc-3.2.3/gcc/config/mips/mips.md 2002-11-11 01:57:14.000000000 -0400
  2456. +++ gcc-3.2.3/gcc/config/mips/mips.md 2015-08-10 16:15:12 +0300
  2457. @@ -84,11 +84,11 @@
  2458. ;; nop no operation
  2459.  
  2460. (define_attr "type"
  2461. - "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
  2462. + "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop,mmi,mmi_mul,mmi_div,vmm_mul,vmm_div"
  2463. (const_string "unknown"))
  2464.  
  2465. ;; Main data type used by the insn
  2466. -(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
  2467. +(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,FPSW" (const_string "unknown"))
  2468.  
  2469. ;; Length (in # of bytes). A conditional branch is allowed only to a
  2470. ;; location within a signed 18-bit offset of the delay slot. If that
  2471. @@ -121,7 +121,7 @@
  2472.  
  2473. ;; ??? Fix everything that tests this attribute.
  2474. (define_attr "cpu"
  2475. - "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000,r4kc,r5kc,r20kc"
  2476. + "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r5900,r8000,r4kc,r5kc,r20kc"
  2477. (const (symbol_ref "mips_cpu_attr")))
  2478.  
  2479. ;; Does the instruction have a mandatory delay slot?
  2480. @@ -206,7 +206,7 @@
  2481.  
  2482. (define_function_unit "memory" 1 0
  2483. (and (eq_attr "type" "load")
  2484. - (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
  2485. + (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000,r5900"))
  2486. 3 0)
  2487.  
  2488. (define_function_unit "memory" 1 0
  2489. @@ -214,17 +214,20 @@
  2490. (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
  2491. 2 0)
  2492.  
  2493. -(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
  2494. +(define_function_unit "memory" 1 0
  2495. + (and (eq_attr "type" "store") (eq_attr "cpu" "!r5900")) 1 0)
  2496.  
  2497. -(define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
  2498. +(define_function_unit "memory" 1 0
  2499. + (and (eq_attr "type" "xfer") (eq_attr "cpu" "!r5900")) 2 0)
  2500.  
  2501. (define_function_unit "imuldiv" 1 0
  2502. - (eq_attr "type" "hilo")
  2503. + (and (eq_attr "type" "hilo")
  2504. + (eq_attr "cpu" "!r5900"))
  2505. 1 3)
  2506.  
  2507. (define_function_unit "imuldiv" 1 0
  2508. (and (eq_attr "type" "imul")
  2509. - (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
  2510. + (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000,r5900"))
  2511. 17 17)
  2512.  
  2513. ;; On them mips16, we want to stronly discourage a mult from appearing
  2514. @@ -276,7 +279,7 @@
  2515.  
  2516. (define_function_unit "imuldiv" 1 0
  2517. (and (eq_attr "type" "idiv")
  2518. - (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
  2519. + (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000,r5900"))
  2520. 38 38)
  2521.  
  2522. (define_function_unit "imuldiv" 1 0
  2523. @@ -333,7 +336,7 @@
  2524. ;; instructions to be processed in the "imuldiv" unit.
  2525.  
  2526. (define_function_unit "adder" 1 1
  2527. - (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))
  2528. + (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000,r5900"))
  2529. 3 0)
  2530.  
  2531. (define_function_unit "adder" 1 1
  2532. @@ -345,7 +348,7 @@
  2533. 1 0)
  2534.  
  2535. (define_function_unit "adder" 1 1
  2536. - (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300"))
  2537. + (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5900"))
  2538. 4 0)
  2539.  
  2540. (define_function_unit "adder" 1 1
  2541. @@ -358,7 +361,7 @@
  2542.  
  2543. (define_function_unit "adder" 1 1
  2544. (and (eq_attr "type" "fabs,fneg")
  2545. - (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
  2546. + (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000,r5900"))
  2547. 2 0)
  2548.  
  2549. (define_function_unit "adder" 1 1
  2550. @@ -368,7 +371,7 @@
  2551. (define_function_unit "mult" 1 1
  2552. (and (eq_attr "type" "fmul")
  2553. (and (eq_attr "mode" "SF")
  2554. - (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
  2555. + (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000,r5900")))
  2556. 7 0)
  2557.  
  2558. (define_function_unit "mult" 1 1
  2559. @@ -388,7 +391,7 @@
  2560.  
  2561. (define_function_unit "mult" 1 1
  2562. (and (eq_attr "type" "fmul")
  2563. - (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")))
  2564. + (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000,r5900")))
  2565. 8 0)
  2566.  
  2567. (define_function_unit "mult" 1 1
  2568. @@ -404,7 +407,7 @@
  2569. (define_function_unit "divide" 1 1
  2570. (and (eq_attr "type" "fdiv")
  2571. (and (eq_attr "mode" "SF")
  2572. - (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
  2573. + (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000,r5900")))
  2574. 23 0)
  2575.  
  2576. (define_function_unit "divide" 1 1
  2577. @@ -430,7 +433,7 @@
  2578. (define_function_unit "divide" 1 1
  2579. (and (eq_attr "type" "fdiv")
  2580. (and (eq_attr "mode" "DF")
  2581. - (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300")))
  2582. + (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5900")))
  2583. 36 0)
  2584.  
  2585. (define_function_unit "divide" 1 1
  2586. @@ -451,7 +454,7 @@
  2587. ;;; ??? Is this number right?
  2588. (define_function_unit "divide" 1 1
  2589. (and (eq_attr "type" "fsqrt")
  2590. - (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
  2591. + (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000,r5900")))
  2592. 54 0)
  2593.  
  2594. (define_function_unit "divide" 1 1
  2595. @@ -467,7 +470,7 @@
  2596. ;;; ??? Is this number right?
  2597. (define_function_unit "divide" 1 1
  2598. (and (eq_attr "type" "fsqrt")
  2599. - (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
  2600. + (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000,r5900")))
  2601. 112 0)
  2602.  
  2603. (define_function_unit "divide" 1 1
  2604. @@ -507,6 +510,63 @@
  2605. (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
  2606. 58 58)
  2608. +;; Using a value immediately after a load causes a one cycle delay.
  2609. +(define_function_unit "memory" 1 0
  2610. + (and (eq_attr "type" "load") (eq_attr "cpu" "r5900")) 2 0)
  2611. +
  2612. +;; The r5900 has a store buffer which can cause an interlock for
  2613. +;; consecutive stores in some cases. So try to separate stores.
  2614. +(define_function_unit "memory" 1 0
  2615. + (and (eq_attr "type" "store") (eq_attr "cpu" "r5900")) 2 1)
  2616. +
  2617. +;; Transfer to/from coprocessor. This is just a guess. There may or
  2618. +;; may not be an interlock for such transfers.
  2619. +(define_function_unit "memory" 1 0
  2620. + (and (eq_attr "type" "xfer") (eq_attr "cpu" "r5900")) 2 0)
  2621. +
  2622. +;; The r5900 has two independent ALUs.
  2623. +;; XXX: MM instructions take up both ALUs, work that out properly here
  2624. +(define_function_unit "alu" 2 0
  2625. + (and (eq_attr "type" "move,arith,darith,icmp,nop,mmi,mmi_mul,mmi_div")
  2626. + (eq_attr "cpu" "r5900")) 1 0)
  2627. +
  2628. +;; It also has a seperate branch unit.
  2629. +(define_function_unit "branch" 1 0
  2630. + (and (eq_attr "type" "branch,jump,call")
  2631. + (eq_attr "cpu" "r5900")) 1 0)
  2632. +
  2633. +;; XXX There is differing data between the architecture manual
  2634. +;; about what these values should be.
  2635. +(define_function_unit "r5900imuldiv" 2 0
  2636. + (and (eq_attr "type" "hilo") (eq_attr "cpu" "r5900")) 1 3)
  2637. +
  2638. +(define_function_unit "r5900imuldiv" 2 0
  2639. + (and (eq_attr "type" "imul") (eq_attr "cpu" "r5900")) 4 2)
  2640. +
  2641. +(define_function_unit "r5900imuldiv" 2 0
  2642. + (and (eq_attr "type" "idiv") (eq_attr "cpu" "r5900")) 37 37)
  2643. +
  2644. +;; The r5900 FP unit has three independent units.
  2645. +;; fmac -- all computational instructions except fdiv, fsqrt, rsqrt
  2646. +;; fdiv -- fdiv, fsqrt, rsqrt
  2647. +;; load/store -- load store and transfer unit
  2648. +;;
  2649. +;; It appears that fmac/fdiv can dual issue with load/store.
  2650. +(define_function_unit "fmac" 1 0
  2651. + (and (eq_attr "type" "fadd,fmul,fmadd,fabs,fneg,fcmp,fcvt")
  2652. + (eq_attr "cpu" "r5900")) 3 0)
  2653. +
  2654. +(define_function_unit "fdiv" 1 1
  2655. + (and (eq_attr "type" "fdiv,fsqrt,frsqrt") (eq_attr "cpu" "r5900")) 6 0)
  2656. +
  2657. +;; And now a few fake units to encourage dual issue.
  2658. +;; We can only issue one operation to the FPU per cycle.
  2659. +(define_function_unit "flop" 1 0
  2660. + (and (eq_attr "type"
  2661. + "fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,xfer")
  2662. + (eq_attr "cpu" "r5900")) 1 0)
  2663. +
  2664. +
  2665. ;; The following functional units do not use the cpu type, and use
  2666. ;; much less memory in genattrtab.c.
  2667.  
  2668. @@ -1727,7 +1787,22 @@
  2669. ""
  2670. "
  2671. {
  2672. - if (GENERATE_MULT3_SI || TARGET_MAD)
  2673. + /* mulsi3_mult3_r5900 is just like the other mulsi3_mult3 pattern, except
  2674. + that it has additional alternatives, slightly different output
  2675. + templates and clobbers pseudos instead of scratches.
  2676. +
  2677. + We generate a different pattern merely to keep the sanitize issues from
  2678. + driving us crazy. Long term we may want the other multiply patterns to
  2679. + clobber pseudos instead of scratches. */
  2680. + if (TARGET_MIPS5900)
  2681. + {
  2682. + emit_insn (gen_mulsi3_mult3_r5900 (operands[0], operands[1], operands[2],
  2683. + gen_reg_rtx (SImode),
  2684. + gen_reg_rtx (SImode),
  2685. + gen_reg_rtx (SImode)));
  2686. + DONE;
  2687. + }
  2688. + else if (GENERATE_MULT3_SI || TARGET_MAD)
  2689. emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
  2690. else if (!TARGET_MIPS4000 || TARGET_MIPS16)
  2691. emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
  2692. @@ -1736,6 +1811,23 @@
  2693. DONE;
  2694. }")
  2695.  
  2696. +(define_insn "mulsi3_mult3_r5900"
  2697. + [(set (match_operand:SI 0 "register_operand" "=d,l,d,v")
  2698. + (mult:SI (match_operand:SI 1 "register_operand" "d,d,d,d")
  2699. + (match_operand:SI 2 "register_operand" "d,d,d,d")))
  2700. + (clobber (match_operand:SI 3 "register_operand" "=h,h,u,u"))
  2701. + (clobber (match_operand:SI 4 "register_operand" "=l,X,v,X"))
  2702. + (clobber (match_operand:SI 5 "register_operand" "=a,a,q,q"))]
  2703. + "TARGET_MIPS5900"
  2704. + "*
  2705. +{
  2706. + if (which_alternative == 1 || which_alternative == 3)
  2707. + return \"mult%H5\\t%1,%2\";
  2708. + return \"mult%H5\\t%0,%1,%2\";
  2709. +}"
  2710. + [(set_attr "type" "imul")
  2711. + (set_attr "mode" "SI")])
  2712. +
  2713. (define_insn "mulsi3_mult3"
  2714. [(set (match_operand:SI 0 "register_operand" "=d,l")
  2715. (mult:SI (match_operand:SI 1 "register_operand" "d,d")
  2716. @@ -1743,8 +1835,8 @@
  2717. (clobber (match_scratch:SI 3 "=h,h"))
  2718. (clobber (match_scratch:SI 4 "=l,X"))
  2719. (clobber (match_scratch:SI 5 "=a,a"))]
  2720. - "GENERATE_MULT3_SI
  2721. - || TARGET_MAD"
  2722. + "(GENERATE_MULT3_SI
  2723. + || TARGET_MAD) && !TARGET_MIPS5900"
  2724. "*
  2725. {
  2726. if (which_alternative == 1)
  2727. @@ -1804,6 +1896,31 @@
  2728. ;; "?" to the constraint is too strong, and causes values to be loaded into
  2729. ;; LO even when that's more costly. For now, using "*d" mostly does the
  2730. ;; trick.
  2731. +
  2732. +;; Like the standard multiply-accumulate, except with more alternatives and
  2733. +;; works with both pipelines.
  2734. +;; XXX: Broken for now.
  2735. +(define_insn "*mul_acc_si_r5900"
  2736. + [(set (match_operand:SI 0 "register_operand" "=l,*d,*d,v,*d,*d")
  2737. + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d,d,d,d")
  2738. + (match_operand:SI 2 "register_operand" "d,d,d,d,d,d"))
  2739. + (match_operand:SI 3 "register_operand" "0,l,*d,0,v,*d")))
  2740. + (clobber (match_scratch:SI 4 "=h,h,h,u,u,u"))
  2741. + (clobber (match_scratch:SI 5 "=X,3,l,X,3,v"))
  2742. + (clobber (match_scratch:SI 6 "=a,a,a,q,q,q"))
  2743. + (clobber (match_scratch:SI 7 "=X,X,d,X,X,d"))]
  2744. + "TARGET_MIPS5900 && !TARGET_MIPS16"
  2745. + "*
  2746. +{
  2747. + static char *const madd[] = { \"madd%H6\\t%1,%2\",
  2748. + \"madd%H6\\t%0,%1,%2\",
  2749. + \"#\" };
  2750. + return madd[which_alternative % 3];
  2751. +}"
  2752. + [(set_attr "type" "imul")
  2753. + (set_attr "mode" "SI")
  2754. + (set_attr "length" "4,4,8,4,4,8")])
  2755. +
  2756. (define_insn "*mul_acc_si"
  2757. [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
  2758. (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
  2759. @@ -1964,7 +2081,7 @@
  2760. (match_operand:DI 2 "register_operand" "d")))
  2761. (clobber (match_scratch:DI 3 "=h"))
  2762. (clobber (match_scratch:DI 4 "=a"))]
  2763. - "TARGET_64BIT"
  2764. + "TARGET_64BIT && !TARGET_MIPS5900"
  2765.  
  2766. "
  2767. {
  2768. @@ -1986,7 +2103,7 @@
  2769. (match_operand:DI 2 "register_operand" "d")))
  2770. (clobber (match_scratch:DI 3 "=h"))
  2771. (clobber (match_scratch:DI 4 "=a"))]
  2772. - "TARGET_64BIT && !TARGET_MIPS4000 && !TARGET_MIPS16"
  2773. + "TARGET_64BIT && !TARGET_MIPS4000 && !TARGET_MIPS16 && !TARGET_MIPS5900"
  2774. "dmult\\t%1,%2"
  2775. [(set_attr "type" "imul")
  2776. (set_attr "mode" "DI")])
  2777. @@ -2032,6 +2149,15 @@
  2778. "
  2779. {
  2780. rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
  2781. + if (TARGET_64BIT && TARGET_MIPS5900)
  2782. + {
  2783. + emit_insn (gen_mulsidi3_64bit_r5900 (operands[0], operands[1],
  2784. + operands[2],
  2785. + dummy, dummy,
  2786. + gen_reg_rtx (DImode),
  2787. + gen_reg_rtx (DImode)));
  2788. + DONE;
  2789. + }
  2790. if (TARGET_64BIT)
  2791. emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
  2792. dummy, dummy));
  2793. @@ -2049,6 +2175,15 @@
  2794. "
  2795. {
  2796. rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
  2797. + if (TARGET_64BIT && TARGET_MIPS5900)
  2798. + {
  2799. + emit_insn (gen_mulsidi3_64bit_r5900 (operands[0], operands[1],
  2800. + operands[2],
  2801. + dummy, dummy,
  2802. + gen_reg_rtx (DImode),
  2803. + gen_reg_rtx (DImode)));
  2804. + DONE;
  2805. + }
  2806. if (TARGET_64BIT)
  2807. emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
  2808. dummy, dummy));
  2809. @@ -2075,6 +2210,25 @@
  2810. [(set_attr "type" "imul")
  2811. (set_attr "mode" "SI")])
  2812.  
  2813. +(define_insn "mulsidi3_64bit_r5900"
  2814. + [(set (match_operand:DI 0 "register_operand" "=a,q")
  2815. + (mult:DI (match_operator:DI 3 "extend_operator"
  2816. + [(match_operand:SI 1 "register_operand" "d,d")])
  2817. + (match_operator:DI 4 "extend_operator"
  2818. + [(match_operand:SI 2 "register_operand" "d,d")])))
  2819. + (clobber (match_operand:DI 5 "register_operand" "=l,v"))
  2820. + (clobber (match_operand:DI 6 "register_operand" "=h,u"))]
  2821. + "TARGET_64BIT && TARGET_MIPS5900
  2822. + && GET_CODE (operands[3]) == GET_CODE (operands[4])"
  2823. + "*
  2824. +{
  2825. + if (GET_CODE (operands[3]) == SIGN_EXTEND)
  2826. + return \"mult%H0\\t%1,%2\";
  2827. + return \"multu%H0\\t%1,%2\";
  2828. +}"
  2829. + [(set_attr "type" "imul")
  2830. + (set_attr "mode" "SI")])
  2831. +
  2832. (define_insn "mulsidi3_64bit"
  2833. [(set (match_operand:DI 0 "register_operand" "=a")
  2834. (mult:DI (match_operator:DI 3 "extend_operator"
  2835. @@ -2111,6 +2265,8 @@
  2836. rtx (*genfn) ();
  2837. #endif
  2838. genfn = gen_xmulsi3_highpart_internal;
  2839. + if (TARGET_MIPS5900)
  2840. + genfn = gen_xmulsi3_highpart_r5900;
  2841. emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
  2842. dummy, dummy2));
  2843. DONE;
  2844. @@ -2132,12 +2288,36 @@
  2845. #else
  2846. rtx (*genfn) ();
  2847. #endif
  2848. + if (TARGET_MIPS5900)
  2849. + genfn = gen_xmulsi3_highpart_r5900;
  2850. genfn = gen_xmulsi3_highpart_internal;
  2851. emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
  2852. dummy, dummy2));
  2853. DONE;
  2854. }")
  2855.  
  2856. +(define_insn "xmulsi3_highpart_r5900"
  2857. + [(set (match_operand:SI 0 "register_operand" "=h,u")
  2858. + (truncate:SI
  2859. + (match_operator:DI 5 "highpart_shift_operator"
  2860. + [(mult:DI (match_operator:DI 3 "extend_operator"
  2861. + [(match_operand:SI 1 "register_operand" "d,d")])
  2862. + (match_operator:DI 4 "extend_operator"
  2863. + [(match_operand:SI 2 "register_operand" "d,d")]))
  2864. + (const_int 32)])))
  2865. + (clobber (match_scratch:SI 6 "=l,v"))
  2866. + (clobber (match_scratch:SI 7 "=a,q"))]
  2867. + "TARGET_MIPS5900 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
  2868. + "*
  2869. +{
  2870. + if (GET_CODE (operands[3]) == SIGN_EXTEND)
  2871. + return \"mult%H0\\t%1,%2\";
  2872. + else
  2873. + return \"multu%H0\\t%1,%2\";
  2874. +}"
  2875. + [(set_attr "type" "imul")
  2876. + (set_attr "mode" "SI")])
  2877. +
  2878. (define_insn "xmulsi3_highpart_internal"
  2879. [(set (match_operand:SI 0 "register_operand" "=h")
  2880. (truncate:SI
  2881. @@ -2168,7 +2348,7 @@
  2882. (const_int 64))))
  2883. (clobber (match_scratch:DI 3 "=l"))
  2884. (clobber (match_scratch:DI 4 "=a"))]
  2885. - "TARGET_64BIT"
  2886. + "TARGET_64BIT && !TARGET_MIPS5900"
  2887. "dmult\\t%1,%2"
  2888. [(set_attr "type" "imul")
  2889. (set_attr "mode" "DI")])
  2890. @@ -2181,7 +2361,7 @@
  2891. (const_int 64))))
  2892. (clobber (match_scratch:DI 3 "=l"))
  2893. (clobber (match_scratch:DI 4 "=a"))]
  2894. - "TARGET_64BIT"
  2895. + "TARGET_64BIT && !TARGET_MIPS5900"
  2896. "dmultu\\t%1,%2"
  2897. [(set_attr "type" "imul")
  2898. (set_attr "mode" "DI")])
  2899. @@ -2397,8 +2577,15 @@
  2900. "optimize"
  2901. "
  2902. {
  2903. + if (TARGET_MIPS5900)
  2904. + {
  2905. + emit_insn (gen_divmodsi4_internal_r5900 (operands[0], operands[1],
  2906. + operands[2], operands[3]));
  2907. + goto zero_div_check;
  2908. + }
  2909. emit_insn (gen_divmodsi4_internal (operands[0], operands[1], operands[2],
  2910. operands[3]));
  2911. +zero_div_check:
  2912. if (!TARGET_NO_CHECK_ZERO_DIV)
  2913. {
  2914. emit_insn (gen_div_trap (operands[2],
  2915. @@ -2421,6 +2608,19 @@
  2916. DONE;
  2917. }")
  2918.  
  2919. +(define_insn "divmodsi4_internal_r5900"
  2920. + [(set (match_operand:SI 0 "register_operand" "=l,v")
  2921. + (div:SI (match_operand:SI 1 "register_operand" "d,d")
  2922. + (match_operand:SI 2 "register_operand" "d,d")))
  2923. + (set (match_operand:SI 3 "register_operand" "=h,u")
  2924. + (mod:SI (match_dup 1)
  2925. + (match_dup 2)))
  2926. + (clobber (match_scratch:SI 4 "=a,q"))]
  2927. + "optimize && TARGET_MIPS5900"
  2928. + "div%H0\\t$0,%1,%2"
  2929. + [(set_attr "type" "idiv")
  2930. + (set_attr "mode" "SI")])
  2931. +
  2932. (define_insn "divmodsi4_internal"
  2933. [(set (match_operand:SI 0 "register_operand" "=l")
  2934. (div:SI (match_operand:SI 1 "register_operand" "d")
  2935. @@ -2429,7 +2629,7 @@
  2936. (mod:SI (match_dup 1)
  2937. (match_dup 2)))
  2938. (clobber (match_scratch:SI 4 "=a"))]
  2939. - "optimize"
  2940. + "optimize && !TARGET_MIPS5900"
  2941. "div\\t$0,%1,%2"
  2942. [(set_attr "type" "idiv")
  2943. (set_attr "mode" "SI")])
  2944. @@ -2444,7 +2644,7 @@
  2945. (clobber (match_scratch:DI 4 "=l"))
  2946. (clobber (match_scratch:DI 5 "=h"))
  2947. (clobber (match_scratch:DI 6 "=a"))]
  2948. - "TARGET_64BIT && optimize"
  2949. + "TARGET_64BIT && optimize && !TARGET_MIPS5900"
  2950. "
  2951. {
  2952. emit_insn (gen_divmoddi4_internal (operands[0], operands[1], operands[2],
  2953. @@ -2477,7 +2677,7 @@
  2954. (mod:DI (match_dup 1)
  2955. (match_dup 2)))
  2956. (clobber (match_scratch:DI 4 "=a"))]
  2957. - "TARGET_64BIT && optimize"
  2958. + "TARGET_64BIT && optimize && !TARGET_MIPS5900"
  2959. "ddiv\\t$0,%1,%2"
  2960. [(set_attr "type" "idiv")
  2961. (set_attr "mode" "SI")])
  2962. @@ -2495,8 +2695,15 @@
  2963. "optimize"
  2964. "
  2965. {
  2966. + if (TARGET_MIPS5900)
  2967. + {
  2968. + emit_insn (gen_udivmodsi4_internal_r5900 (operands[0], operands[1],
  2969. + operands[2], operands[3]));
  2970. + goto zero_div_check;
  2971. + }
  2972. emit_insn (gen_udivmodsi4_internal (operands[0], operands[1], operands[2],
  2973. operands[3]));
  2974. +zero_div_check:
  2975. if (!TARGET_NO_CHECK_ZERO_DIV)
  2976. {
  2977. emit_insn (gen_div_trap (operands[2],
  2978. @@ -2507,6 +2714,19 @@
  2979. DONE;
  2980. }")
  2981.  
  2982. +(define_insn "udivmodsi4_internal_r5900"
  2983. + [(set (match_operand:SI 0 "register_operand" "=l,v")
  2984. + (udiv:SI (match_operand:SI 1 "register_operand" "d,d")
  2985. + (match_operand:SI 2 "register_operand" "d,d")))
  2986. + (set (match_operand:SI 3 "register_operand" "=h,u")
  2987. + (umod:SI (match_dup 1)
  2988. + (match_dup 2)))
  2989. + (clobber (match_scratch:SI 4 "=a,q"))]
  2990. + "optimize && TARGET_MIPS5900"
  2991. + "divu%H0\\t$0,%1,%2"
  2992. + [(set_attr "type" "idiv")
  2993. + (set_attr "mode" "SI")])
  2994. +
  2995. (define_insn "udivmodsi4_internal"
  2996. [(set (match_operand:SI 0 "register_operand" "=l")
  2997. (udiv:SI (match_operand:SI 1 "register_operand" "d")
  2998. @@ -2515,7 +2735,7 @@
  2999. (umod:SI (match_dup 1)
  3000. (match_dup 2)))
  3001. (clobber (match_scratch:SI 4 "=a"))]
  3002. - "optimize"
  3003. + "optimize && !TARGET_MIPS5900"
  3004. "divu\\t$0,%1,%2"
  3005. [(set_attr "type" "idiv")
  3006. (set_attr "mode" "SI")])
  3007. @@ -2530,7 +2750,7 @@
  3008. (clobber (match_scratch:DI 4 "=l"))
  3009. (clobber (match_scratch:DI 5 "=h"))
  3010. (clobber (match_scratch:DI 6 "=a"))]
  3011. - "TARGET_64BIT && optimize"
  3012. + "TARGET_64BIT && optimize && !TARGET_MIPS5900"
  3013. "
  3014. {
  3015. emit_insn (gen_udivmoddi4_internal (operands[0], operands[1], operands[2],
  3016. @@ -2553,7 +2773,7 @@
  3017. (umod:DI (match_dup 1)
  3018. (match_dup 2)))
  3019. (clobber (match_scratch:DI 4 "=a"))]
  3020. - "TARGET_64BIT && optimize"
  3021. + "TARGET_64BIT && optimize && !TARGET_MIPS5900"
  3022. "ddivu\\t$0,%1,%2"
  3023. [(set_attr "type" "idiv")
  3024. (set_attr "mode" "SI")])
  3025. @@ -2651,6 +2871,7 @@
  3026. [(set_attr "type" "unknown")
  3027. (set_attr "length" "12")])
  3028.  
  3029. +;; Add r5900-specific div here.
  3030. (define_expand "divsi3"
  3031. [(set (match_operand:SI 0 "register_operand" "=l")
  3032. (div:SI (match_operand:SI 1 "register_operand" "d")
  3033. @@ -2700,7 +2921,7 @@
  3034. (match_operand:DI 2 "se_register_operand" "d")))
  3035. (clobber (match_scratch:DI 3 "=h"))
  3036. (clobber (match_scratch:DI 4 "=a"))]
  3037. - "TARGET_64BIT && !optimize"
  3038. + "TARGET_64BIT && !optimize && !TARGET_MIPS5900"
  3039. "
  3040. {
  3041. emit_insn (gen_divdi3_internal (operands[0], operands[1], operands[2]));
  3042. @@ -2730,11 +2951,12 @@
  3043. (match_operand:DI 2 "se_nonmemory_operand" "di")))
  3044. (clobber (match_scratch:SI 3 "=h"))
  3045. (clobber (match_scratch:SI 4 "=a"))]
  3046. - "TARGET_64BIT && !optimize"
  3047. + "TARGET_64BIT && !optimize && !TARGET_MIPS5900"
  3048. "ddiv\\t$0,%1,%2"
  3049. [(set_attr "type" "idiv")
  3050. (set_attr "mode" "DI")])
  3051.  
  3052. +;; XXX: add r5900-specific support here
  3053. (define_expand "modsi3"
  3054. [(set (match_operand:SI 0 "register_operand" "=h")
  3055. (mod:SI (match_operand:SI 1 "register_operand" "d")
  3056. @@ -2784,7 +3006,7 @@
  3057. (match_operand:DI 2 "se_register_operand" "d")))
  3058. (clobber (match_scratch:DI 3 "=l"))
  3059. (clobber (match_scratch:DI 4 "=a"))]
  3060. - "TARGET_64BIT && !optimize"
  3061. + "TARGET_64BIT && !optimize && !TARGET_MIPS5900"
  3062. "
  3063. {
  3064. emit_insn (gen_moddi3_internal (operands[0], operands[1], operands[2]));
  3065. @@ -2814,11 +3036,12 @@
  3066. (match_operand:DI 2 "se_nonmemory_operand" "di")))
  3067. (clobber (match_scratch:SI 3 "=l"))
  3068. (clobber (match_scratch:SI 4 "=a"))]
  3069. - "TARGET_64BIT && !optimize"
  3070. + "TARGET_64BIT && !optimize && !TARGET_MIPS5900"
  3071. "ddiv\\t$0,%1,%2"
  3072. [(set_attr "type" "idiv")
  3073. (set_attr "mode" "DI")])
  3074.  
  3075. +;; XXX: Add r5900-specific support here
  3076. (define_expand "udivsi3"
  3077. [(set (match_operand:SI 0 "register_operand" "=l")
  3078. (udiv:SI (match_operand:SI 1 "register_operand" "d")
  3079. @@ -2856,7 +3079,7 @@
  3080. (match_operand:DI 2 "se_register_operand" "di")))
  3081. (clobber (match_scratch:DI 3 "=h"))
  3082. (clobber (match_scratch:DI 4 "=a"))]
  3083. - "TARGET_64BIT && !optimize"
  3084. + "TARGET_64BIT && !optimize && !TARGET_MIPS5900"
  3085. "
  3086. {
  3087. emit_insn (gen_udivdi3_internal (operands[0], operands[1], operands[2]));
  3088. @@ -2876,11 +3099,12 @@
  3089. (match_operand:DI 2 "se_nonmemory_operand" "di")))
  3090. (clobber (match_scratch:SI 3 "=h"))
  3091. (clobber (match_scratch:SI 4 "=a"))]
  3092. - "TARGET_64BIT && !optimize"
  3093. + "TARGET_64BIT && !optimize && !TARGET_MIPS5900"
  3094. "ddivu\\t$0,%1,%2"
  3095. [(set_attr "type" "idiv")
  3096. (set_attr "mode" "DI")])
  3097.  
  3098. +;; XXX: add r5900-specific support here
  3099. (define_expand "umodsi3"
  3100. [(set (match_operand:SI 0 "register_operand" "=h")
  3101. (umod:SI (match_operand:SI 1 "register_operand" "d")
  3102. @@ -2918,7 +3142,7 @@
  3103. (match_operand:DI 2 "se_register_operand" "di")))
  3104. (clobber (match_scratch:DI 3 "=l"))
  3105. (clobber (match_scratch:DI 4 "=a"))]
  3106. - "TARGET_64BIT && !optimize"
  3107. + "TARGET_64BIT && !optimize && !TARGET_MIPS5900"
  3108. "
  3109. {
  3110. emit_insn (gen_umoddi3_internal (operands[0], operands[1], operands[2]));
  3111. @@ -2938,7 +3162,7 @@
  3112. (match_operand:DI 2 "se_nonmemory_operand" "di")))
  3113. (clobber (match_scratch:SI 3 "=l"))
  3114. (clobber (match_scratch:SI 4 "=a"))]
  3115. - "TARGET_64BIT && !optimize"
  3116. + "TARGET_64BIT && !optimize && !TARGET_MIPS5900"
  3117. "ddivu\\t$0,%1,%2"
  3118. [(set_attr "type" "idiv")
  3119. (set_attr "mode" "DI")])
  3120. @@ -2979,7 +3203,7 @@
  3121. [(set (match_operand:SF 0 "register_operand" "=f")
  3122. (div:SF (match_operand:SF 1 "const_float_1_operand" "")
  3123. (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
  3124. - "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
  3125. + "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_MIPS5900 && flag_unsafe_math_optimizations"
  3126. "rsqrt.s\\t%0,%2"
  3127. [(set_attr "type" "fsqrt")
  3128. (set_attr "mode" "SF")])
  3129. @@ -3061,6 +3285,37 @@
  3130. (set_attr "mode" "SF")])
  3131.  
  3133. +;; ....................
  3134. +;;
  3135. +;; MIN, MAX
  3136. +;;
  3137. +;; ....................
  3138. +
  3139. +(define_insn "minsf3"
  3140. + [(set (match_operand:SF 0 "register_operand" "=f")
  3141. + (if_then_else (lt:SF
  3142. + (match_operand:SF 1 "register_operand" "f")
  3143. + (match_operand:SF 2 "register_operand" "f"))
  3144. + (match_dup 1)
  3145. + (match_dup 2)))]
  3146. + "TARGET_HARD_FLOAT && TARGET_MIPS5900"
  3147. + "min.s\\t%0,%1,%2"
  3148. + [(set_attr "type" "fadd")
  3149. + (set_attr "mode" "SF")])
  3150. +
  3151. +(define_insn "maxsf3"
  3152. + [(set (match_operand:SF 0 "register_operand" "=f")
  3153. + (if_then_else (gt:SF
  3154. + (match_operand:SF 1 "register_operand" "f")
  3155. + (match_operand:SF 2 "register_operand" "f"))
  3156. + (match_dup 1)
  3157. + (match_dup 2)))]
  3158. + "TARGET_HARD_FLOAT && TARGET_MIPS5900"
  3159. + "max.s\\t%0,%1,%2"
  3160. + [(set_attr "type" "fadd")
  3161. + (set_attr "mode" "SF")])
  3162. +
  3163. +
  3164. ;;
  3165. ;; ....................
  3166. ;;
  3167. @@ -3081,6 +3336,38 @@
  3168. dslots_jump_filled += 2;
  3169. operands[4] = const0_rtx;
  3170.  
  3171. + if (TARGET_MIPS5900 && !TARGET_NO_LENGTHEN_LOOP ) {
  3172. + if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
  3173. + return \"%(\\
  3174. +move\\t%0,%z4\\n\\
  3175. +\\tbeq\\t%1,%z4,2f\\n\\
  3176. +1:\\tand\\t%2,%1,0x0001\\n\\
  3177. +\\taddu\\t%0,%0,1\\n\\
  3178. +\\tbne\\t%2,%z4,2f\\n\\
  3179. +\\tsrl\\t%1,%1,1\\n\\
  3180. +\\n\\
  3181. +\\tand\\t%2,%1,0x0001\\n\\
  3182. +\\taddu\\t%0,%0,1\\n\\
  3183. +\\tbeq\\t%2,%z4,1b\\n\\
  3184. +\\tsrl\\t%1,%1,1\\n\\
  3185. +2:%)\";
  3186. +
  3187. + return \"%(\\
  3188. +move\\t%0,%z4\\n\\
  3189. +\\tmove\\t%3,%1\\n\\
  3190. +\\tbeq\\t%3,%z4,2f\\n\\
  3191. +1:\\tand\\t%2,%3,0x0001\\n\\
  3192. +\\taddu\\t%0,%0,1\\n\\
  3193. +\\tbne\\t%2,%z4,2f\\n\\
  3194. +\\tsrl\\t%3,%3,1\\n\\
  3195. +\\n\\
  3196. +\\tand\\t%2,%3,0x0001\\n\\
  3197. +\\taddu\\t%0,%0,1\\n\\
  3198. +\\tbeq\\t%2,%z4,1b\\n\\
  3199. +\\tsrl\\t%3,%3,1\\n\\
  3200. +2:%)\";
  3201. + }
  3202. +
  3203. if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
  3204. return \"%(\\
  3205. move\\t%0,%z4\\n\\
  3206. @@ -3103,7 +3390,11 @@
  3207. }"
  3208. [(set_attr "type" "multi")
  3209. (set_attr "mode" "SI")
  3210. - (set_attr "length" "12")])
  3211. + (set (attr "length")
  3212. + (if_then_else (and (ne (const_int 0) (symbol_ref "TARGET_MIPS5900") )
  3213. + (eq (const_int 0) (symbol_ref "TARGET_NO_LENGTHEN_LOOP")))
  3214. + (const_int 44)
  3215. + (const_int 24))) ])
  3216.  
  3217. (define_insn "ffsdi2"
  3218. [(set (match_operand:DI 0 "register_operand" "=&d")
  3219. @@ -3117,6 +3408,38 @@
  3220. dslots_jump_filled += 2;
  3221. operands[4] = const0_rtx;
  3222.  
  3223. + if (TARGET_MIPS5900 && !TARGET_NO_LENGTHEN_LOOP ) {
  3224. + if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
  3225. + return \"%(\\
  3226. +move\\t%0,%z4\\n\\
  3227. +\\tbeq\\t%1,%z4,2f\\n\\
  3228. +1:\\tand\\t%2,%1,0x0001\\n\\
  3229. +\\tdaddu\\t%0,%0,1\\n\\
  3230. +\\tbne\\t%2,%z4,2f\\n\\
  3231. +\\tdsrl\\t%1,%1,1\\n\\
  3232. +\\n\\
  3233. +\\tand\\t%2,%1,0x0001\\n\\
  3234. +\\tdaddu\\t%0,%0,1\\n\\
  3235. +\\tbeq\\t%2,%z4,1b\\n\\
  3236. +\\tdsrl\\t%1,%1,1\\n\\
  3237. +2:%)\";
  3238. +
  3239. + return \"%(\\
  3240. +move\\t%0,%z4\\n\\
  3241. +\\tmove\\t%3,%1\\n\\
  3242. +\\tbeq\\t%3,%z4,2f\\n\\
  3243. +1:\\tand\\t%2,%3,0x0001\\n\\
  3244. +\\tdaddu\\t%0,%0,1\\n\\
  3245. +\\tbne\\t%2,%z4,2f\\n\\
  3246. +\\tdsrl\\t%3,%3,1\\n\\
  3247. +\\n\\
  3248. +\\tand\\t%2,%3,0x0001\\n\\
  3249. +\\tdaddu\\t%0,%0,1\\n\\
  3250. +\\tbeq\\t%2,%z4,1b\\n\\
  3251. +\\tdsrl\\t%3,%3,1\\n\\
  3252. +2:%)\";
  3253. + }
  3254. +
  3255. if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
  3256. return \"%(\\
  3257. move\\t%0,%z4\\n\\
  3258. @@ -3139,7 +3462,11 @@
  3259. }"
  3260. [(set_attr "type" "multi")
  3261. (set_attr "mode" "DI")
  3262. - (set_attr "length" "24")])
  3263. + (set (attr "length")
  3264. + (if_then_else (and (ne (const_int 0) (symbol_ref "TARGET_MIPS5900") )
  3265. + (eq (const_int 0) (symbol_ref "TARGET_NO_LENGTHEN_LOOP")))
  3266. + (const_int 44)
  3267. + (const_int 24))) ])
  3268.  
  3270. ;;
  3271. @@ -3271,6 +3598,18 @@
  3272. (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
  3273. "")
  3274.  
  3275. +(define_insn "one_cmplti2"
  3276. + [(set (match_operand:TI 0 "register_operand" "=d")
  3277. + (not:TI (match_operand:TI 1 "register_operand" "d")))]
  3278. + "TARGET_MIPS5900"
  3279. + "*
  3280. +{
  3281. + operands[2] = const0_rtx;
  3282. + return \"pnor\\t%0,%z2,%1\";
  3283. +}"
  3284. + [(set_attr "type" "mmi")
  3285. + (set_attr "mode" "TI")])
  3286. +
  3288. ;;
  3289. ;; ....................
  3290. @@ -3386,6 +3725,17 @@
  3291. [(set_attr "type" "arith")
  3292. (set_attr "mode" "DI")])
  3293.  
  3294. +(define_insn "andti3"
  3295. + [(set (match_operand:TI 0 "register_operand" "=d,d")
  3296. + (and:TI (match_operand:TI 1 "register_operand" "%0,d")
  3297. + (match_operand:TI 2 "register_operand" "d,d")))]
  3298. + "TARGET_MIPS5900"
  3299. + "@
  3300. + pand\\t%0,%2
  3301. + pand\\t%0,%1,%2"
  3302. + [(set_attr "type" "mmi")
  3303. + (set_attr "mode" "TI")])
  3304. +
  3305. (define_expand "iorsi3"
  3306. [(set (match_operand:SI 0 "register_operand" "=d,d")
  3307. (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
  3308. @@ -3477,6 +3827,17 @@
  3309. (set (subreg:SI (match_dup 0) 4) (ior:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))]
  3310. "")
  3311.  
  3312. +(define_insn "iorti3"
  3313. + [(set (match_operand:TI 0 "register_operand" "=d,d")
  3314. + (ior:TI (match_operand:TI 1 "register_operand" "%0,d")
  3315. + (match_operand:TI 2 "register_operand" "d,d")))]
  3316. + "TARGET_MIPS5900"
  3317. + "@
  3318. + por\\t%0,%2
  3319. + por\\t%0,%1,%2"
  3320. + [(set_attr "type" "mmi")
  3321. + (set_attr "mode" "TI")])
  3322. +
  3323. (define_expand "xorsi3"
  3324. [(set (match_operand:SI 0 "register_operand" "=d,d")
  3325. (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
  3326. @@ -3591,6 +3952,17 @@
  3327. [(set_attr "type" "arith")
  3328. (set_attr "mode" "DI")])
  3329.  
  3330. +(define_insn "xorti3"
  3331. + [(set (match_operand:TI 0 "register_operand" "=d,d")
  3332. + (xor:TI (match_operand:TI 1 "register_operand" "%0,d")
  3333. + (match_operand:TI 2 "register_operand" "d,d")))]
  3334. + "TARGET_MIPS5900"
  3335. + "@
  3336. + pxor\\t%0,%2
  3337. + pxor\\t%0,%1,%2"
  3338. + [(set_attr "type" "mmi")
  3339. + (set_attr "mode" "TI")])
  3340. +
  3341. (define_insn "*norsi3"
  3342. [(set (match_operand:SI 0 "register_operand" "=d")
  3343. (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
  3344. @@ -3632,6 +4004,18 @@
  3345. (set (subreg:SI (match_dup 0) 4) (and:SI (not:SI (subreg:SI (match_dup 1) 4)) (not:SI (subreg:SI (match_dup 2) 4))))]
  3346. "")
  3348. +(define_insn "*norti3"
  3349. + [(set (match_operand:TI 0 "register_operand" "=d,d")
  3350. + (and:TI (not:TI (match_operand:TI 1 "register_operand" "%0,d"))
  3351. + (not:TI (match_operand:TI 2 "register_operand" "d,d"))))]
  3352. + "TARGET_MIPS5900"
  3353. + "@
  3354. + pnor\\t%0,%2
  3355. + pnor\\t%0,%1,%2"
  3356. + [(set_attr "type" "mmi")
  3357. + (set_attr "mode" "TI")])
  3358. +
  3359. +
  3360. ;;
  3361. ;; ....................
  3362. ;;
  3363. @@ -4073,7 +4457,7 @@
  3364.  
  3365. (define_insn "extendsidi2"
  3366. [(set (match_operand:DI 0 "register_operand" "=d,y,d,*d,d,d")
  3367. - (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,d,y,*x,R,m")))]
  3368. + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,d,y,*x*w,R,m")))]
  3369. "TARGET_64BIT"
  3370. "* return mips_move_1word (operands, insn, FALSE);"
  3371. [(set_attr "type" "move,move,move,hilo,load,load")
  3372. @@ -4299,6 +4683,21 @@
  3373. {
  3374. rtx xoperands[10];
  3375.  
  3376. + /* trunc.w.s isn't implemented on the r5900, but cvt.w.s */
  3377. + /* truncates, so use it here. */
  3378. + if (TARGET_MIPS5900)
  3379. + {
  3380. + if (which_alternative == 1)
  3381. + return \"cvt.w.s %0,%1\";
  3382. +
  3383. + output_asm_insn (\"cvt.w.s %3,%1\", operands);
  3384. +
  3385. + xoperands[0] = operands[0];
  3386. + xoperands[1] = operands[3];
  3387. + output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
  3388. + return \"\";
  3389. + }
  3390. +
  3391. if (which_alternative == 1)
  3392. return \"trunc.w.s %0,%1,%2\";
  3393.  
  3394. @@ -4912,6 +5311,86 @@
  3395. [(set_attr "type" "arith")
  3396. (set_attr "mode" "SI")])
  3397.  
  3398. +;; 128-bit integer moves
  3399. +
  3400. +;; Unlike most other insns, the move insns can't be split with
  3401. +;; different predicates, because register spilling and other parts of
  3402. +;; the compiler, have memoized the insn number already.
  3403. +
  3404. +(define_expand "movti"
  3405. + [(set (match_operand:TI 0 "nonimmediate_operand" "")
  3406. + (match_operand:TI 1 "general_operand" ""))]
  3407. + "TARGET_MIPS5900"
  3408. + "
  3409. +{
  3410. + /* I think this code is unnecessary since we'll never split when
  3411. + the mode is larger than UNITS_PER_WORD. */
  3412. + if (mips_split_addresses && mips_check_split (operands[1], TImode))
  3413. + {
  3414. + enum machine_mode mode = GET_MODE (operands[0]);
  3415. + rtx tem = ((reload_in_progress | reload_completed)
  3416. + ? operands[0] : gen_reg_rtx (mode));
  3417. +
  3418. + emit_insn (gen_rtx (SET, VOIDmode, tem,
  3419. + gen_rtx (HIGH, mode, operands[1])));
  3420. +
  3421. + operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]);
  3422. + }
  3423. +
  3424. + /* If we are generating embedded PIC code, and we are referring to a
  3425. + symbol in the .text section, we must use an offset from the start
  3426. + of the function.
  3427. +
  3428. + For now we abort this case on the R5900. */
  3429. + if (TARGET_EMBEDDED_PIC
  3430. + && (GET_CODE (operands[1]) == LABEL_REF
  3431. + || (GET_CODE (operands[1]) == SYMBOL_REF
  3432. + && ! SYMBOL_REF_FLAG (operands[1]))))
  3433. + abort ();
  3434. +
  3435. + /* If operands[1] is a constant address illegal for pic, then we need to
  3436. + handle it just like LEGITIMIZE_ADDRESS does.
  3437. + For now we abort this case on the R5900. */
  3438. + if (flag_pic && pic_address_needs_scratch (operands[1]))
  3439. + abort ();
  3440. +
  3441. + /* Make operand1 a register if it isn't already. */
  3442. + if ((reload_in_progress | reload_completed) == 0
  3443. + && !register_operand (operands[0], TImode)
  3444. + && !register_operand (operands[1], TImode)
  3445. + && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
  3446. + && operands[1] != CONST0_RTX (TImode))
  3447. + {
  3448. + rtx temp = force_reg (TImode, operands[1]);
  3449. + emit_move_insn (operands[0], temp);
  3450. + DONE;
  3451. + }
  3452. +}")
  3453. +
  3454. +(define_insn "movti_internal"
  3455. + [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,R,m,d,d,d,d,d")
  3456. + (match_operand:TI 1 "movti_operand" "d,R,m,d,d,J,K,L,M,i"))]
  3457. + "TARGET_MIPS5900
  3458. + && (register_operand (operands[0], TImode)
  3459. + || se_register_operand (operands[1], TImode)
  3460. + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
  3461. + || operands[1] == CONST0_RTX (TImode))"
  3462. + "@
  3463. + por %0,$0,%1
  3464. + lq %0,%1
  3465. + lq %0,%1
  3466. + sq %1,%0
  3467. + sq %1,%0
  3468. + por %0,%.,%.
  3469. + por\\t%0,%.,%.\;li\\t%0,%1 \\t\\t\\t# ori
  3470. + por\\t%0,%.,%.\;li\\t%0,%1 \\t\\t\\t# lui
  3471. + por\\t%0,%.,%.\;dli\\t%0,%1 \\t\\t\\t# general li macro
  3472. + dli\\t%0,%M1\;pcpyld\\t%0,%0,%.\;dli\\t%0,%L1"
  3473. + [(set_attr "type" "mmi,load,load,store,store,mmi,mmi,mmi,mmi,mmi")
  3474. + (set_attr "mode" "TI")
  3475. +;; The general li macro on a 64 bit machine can be up to 7 instructions long.
  3476. + (set_attr "length" "4,4,4,4,4,4,16,16,32,60")])
  3477. +
  3478. ;; 64-bit integer moves
  3479.  
  3480. ;; Unlike most other insns, the move insns can't be split with
  3481. @@ -5039,7 +5518,7 @@
  3482. (set_attr "length" "4,8")])
  3483.  
  3484. (define_insn "movdi_internal"
  3485. - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x,*d,*x")
  3486. + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x*w,*d,*x*w")
  3487. (match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,J,*x,*d"))]
  3488. "!TARGET_64BIT && !TARGET_MIPS16
  3489. && (register_operand (operands[0], DImode)
  3490. @@ -5075,8 +5554,8 @@
  3491. "")
  3492.  
  3493. (define_insn "movdi_internal2"
  3494. - [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*x,*d,*x,*a")
  3495. - (match_operand:DI 1 "movdi_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,J,*x,*d,*J"))]
  3496. + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*x*w,*d,*x*w,*a*q")
  3497. + (match_operand:DI 1 "movdi_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,J,*x*w,*d,*J"))]
  3498. "TARGET_64BIT && !TARGET_MIPS16
  3499. && (register_operand (operands[0], DImode)
  3500. || se_register_operand (operands[1], DImode)
  3501. @@ -5089,7 +5568,7 @@
  3502.  
  3503. (define_insn ""
  3504. [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,R,m,*d")
  3505. - (match_operand:DI 1 "movdi_operand" "d,d,y,K,N,s,R,m,d,d,*x"))]
  3506. + (match_operand:DI 1 "movdi_operand" "d,d,y,K,N,s,R,m,d,d,*x*w"))]
  3507. "TARGET_64BIT && TARGET_MIPS16
  3508. && (register_operand (operands[0], DImode)
  3509. || se_register_operand (operands[1], DImode))"
  3510. @@ -5180,7 +5659,7 @@
  3511. ? REGNO (operands[2]) + 1
  3512. : REGNO (operands[2])));
  3513.  
  3514. - if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
  3515. + if (GET_CODE (operands[0]) == REG && ( REGNO (operands[0]) == HILO_REGNUM || REGNO (operands[0]) == HILO1_REGNUM ) )
  3516. {
  3517. if (GET_CODE (operands[1]) == MEM)
  3518. {
  3519. @@ -5203,28 +5682,45 @@
  3520. lo_word = memword;
  3521. }
  3522. emit_move_insn (scratch, hi_word);
  3523. + if( REGNO (operands[0]) == HILO_REGNUM )
  3524. emit_move_insn (gen_rtx_REG (SImode, 64), scratch);
  3525. + else
  3526. + emit_move_insn (gen_rtx_REG (SImode, 76), scratch);
  3527. emit_move_insn (scratch, lo_word);
  3528. + if( REGNO (operands[0]) == HILO_REGNUM )
  3529. emit_move_insn (gen_rtx (REG, SImode, 65), scratch);
  3530. + else
  3531. + emit_move_insn (gen_rtx (REG, SImode, 77), scratch);
  3532. emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
  3533. }
  3534. else
  3535. {
  3536. emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
  3537. + if( REGNO (operands[0]) == HILO_REGNUM )
  3538. emit_insn (gen_movdi (gen_rtx_REG (DImode, 64), scratch));
  3539. + else
  3540. + emit_insn (gen_movdi (gen_rtx_REG (DImode, 76), scratch));
  3541. emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
  3542. emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
  3543. + if( REGNO (operands[0]) == HILO_REGNUM )
  3544. emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
  3545. - emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
  3546. + else
  3547. + emit_insn (gen_movdi (gen_rtx (REG, DImode, 77), scratch));
  3548. }
  3549. DONE;
  3550. }
  3551. - if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
  3552. + if (GET_CODE (operands[1]) == REG && ( REGNO (operands[1]) == HILO_REGNUM || REGNO (operands[1]) == HILO1_REGNUM ) )
  3553. {
  3554. + if( REGNO (operands[1]) == HILO_REGNUM )
  3555. emit_insn (gen_movdi (scratch, gen_rtx_REG (DImode, 65)));
  3556. + else
  3557. + emit_insn (gen_movdi (scratch, gen_rtx_REG (DImode, 76)));
  3558. emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
  3559. emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
  3560. + if( REGNO (operands[1]) == HILO_REGNUM )
  3561. emit_insn (gen_movdi (operands[0], gen_rtx_REG (DImode, 64)));
  3562. + else
  3563. + emit_insn (gen_movdi (operands[0], gen_rtx_REG (DImode, 77)));
  3564. emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
  3565. emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
  3566. emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
  3567. @@ -5242,7 +5738,7 @@
  3568. ;; use a TImode scratch reg.
  3569.  
  3570. (define_expand "reload_outdi"
  3571. - [(set (match_operand:DI 0 "general_operand" "=b")
  3572. + [(set (match_operand:DI 0 "" "=b")
  3573. (match_operand:DI 1 "se_register_operand" "b"))
  3574. (clobber (match_operand:TI 2 "register_operand" "=&d"))]
  3575. "TARGET_64BIT"
  3576. @@ -5250,17 +5746,23 @@
  3577. {
  3578. rtx scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
  3579.  
  3580. - if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
  3581. + if (GET_CODE (operands[0]) == REG && ( REGNO (operands[0]) == HILO_REGNUM || REGNO (operands[0]) == HILO1_REGNUM ) )
  3582. {
  3583. emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
  3584. + if( REGNO (operands[0]) == HILO_REGNUM )
  3585. emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch));
  3586. + else
  3587. + emit_insn (gen_movdi (gen_rtx (REG, DImode, 76), scratch));
  3588. emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
  3589. emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
  3590. + if( REGNO (operands[0]) == HILO_REGNUM )
  3591. emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
  3592. + else
  3593. + emit_insn (gen_movdi (gen_rtx (REG, DImode, 77), scratch));
  3594. emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[0]), 2));
  3595. DONE;
  3596. }
  3597. - if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
  3598. + if (GET_CODE (operands[1]) == REG && ( REGNO (operands[1]) == HILO_REGNUM || REGNO (operands[1]) == HILO1_REGNUM ) )
  3599. {
  3600. if (GET_CODE (operands[0]) == MEM)
  3601. {
  3602. @@ -5282,9 +5784,15 @@
  3603. hi_word = offword;
  3604. lo_word = memword;
  3605. }
  3606. + if( REGNO (operands[1]) == HILO_REGNUM )
  3607. emit_move_insn (scratch, gen_rtx_REG (SImode, 64));
  3608. + else
  3609. + emit_move_insn (scratch, gen_rtx_REG (SImode, 76));
  3610. emit_move_insn (hi_word, scratch);
  3611. + if( REGNO (operands[1]) == HILO_REGNUM )
  3612. emit_move_insn (scratch, gen_rtx_REG (SImode, 65));
  3613. + else
  3614. + emit_move_insn (scratch, gen_rtx_REG (SImode, 77));
  3615. emit_move_insn (lo_word, scratch);
  3616. emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
  3617. }
  3618. @@ -5294,10 +5802,16 @@
  3619. and hence we can not directly move from the HILO register
  3620. into it. */
  3621. rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
  3622. + if( REGNO (operands[1]) == HILO_REGNUM )
  3623. emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
  3624. + else
  3625. + emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 77)));
  3626. emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
  3627. emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
  3628. + if( REGNO (operands[1]) == HILO_REGNUM )
  3629. emit_insn (gen_movdi (scratch2, gen_rtx (REG, DImode, 64)));
  3630. + else
  3631. + emit_insn (gen_movdi (scratch2, gen_rtx (REG, DImode, 76)));
  3632. emit_insn (gen_ashldi3 (scratch2, scratch2, GEN_INT (32)));
  3633. emit_insn (gen_iordi3 (scratch, scratch, scratch2));
  3634. emit_insn (gen_movdi (operands[0], scratch));
  3635. @@ -5305,10 +5819,16 @@
  3636. }
  3637. else
  3638. {
  3639. + if( REGNO (operands[1]) == HILO_REGNUM )
  3640. emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
  3641. + else
  3642. + emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 77)));
  3643. emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
  3644. emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
  3645. + if( REGNO (operands[1]) == HILO_REGNUM )
  3646. emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
  3647. + else
  3648. + emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 76)));
  3649. emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
  3650. emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
  3651. emit_insn (gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, operands[1]), 2));
  3652. @@ -5468,8 +5988,8 @@
  3653. ;; in FP registers (off by default, use -mdebugh to enable).
  3654.  
  3655. (define_insn "movsi_internal1"
  3656. - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*x,*d,*d")
  3657. - (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x,*a"))]
  3658. + [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x*w,*x*w,*d,*d")
  3659. + (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x*w,*a*q"))]
  3660. "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
  3661. && (register_operand (operands[0], SImode)
  3662. || register_operand (operands[1], SImode)
  3663. @@ -5480,8 +6000,8 @@
  3664. (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,4,8,4,8,4,4,4,4")])
  3665.  
  3666. (define_insn "movsi_internal2"
  3667. - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d")
  3668. - (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a"))]
  3669. + [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, d, d,d,d, R, m,*d,*z,*x*w,*d,*x*w,*d")
  3670. + (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x*w,*d,*a*q"))]
  3671. "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
  3672. && (register_operand (operands[0], SImode)
  3673. || register_operand (operands[1], SImode)
  3674. @@ -5764,7 +6284,7 @@
  3675.  
  3676. ;; This insn is for the unspec delay for HILO.
  3677.  
  3678. -(define_insn "*HILO_delay"
  3679. +(define_insn "HILO_delay"
  3680. [(unspec [(match_operand 0 "register_operand" "=b")] 2 )]
  3681. ""
  3682. ""
  3683. @@ -5937,8 +6457,8 @@
  3684. ;; in FP registers (off by default, use -mdebugh to enable).
  3685.  
  3686. (define_insn "movhi_internal1"
  3687. - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d")
  3688. - (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
  3689. + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x*w,*d")
  3690. + (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x*w"))]
  3691. "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
  3692. && (register_operand (operands[0], HImode)
  3693. || register_operand (operands[1], HImode)
  3694. @@ -5949,8 +6469,8 @@
  3695. (set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
  3696.  
  3697. (define_insn "movhi_internal2"
  3698. - [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
  3699. - (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
  3700. + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x*w,*d")
  3701. + (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x*w"))]
  3702. "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
  3703. && (register_operand (operands[0], HImode)
  3704. || register_operand (operands[1], HImode)
  3705. @@ -5962,7 +6482,7 @@
  3706.  
  3707. (define_insn ""
  3708. [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
  3709. - (match_operand:HI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))]
  3710. + (match_operand:HI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x*w"))]
  3711. "TARGET_MIPS16
  3712. && (register_operand (operands[0], HImode)
  3713. || register_operand (operands[1], HImode))"
  3714. @@ -6059,8 +6579,8 @@
  3715. ;; in FP registers (off by default, use -mdebugh to enable).
  3716.  
  3717. (define_insn "movqi_internal1"
  3718. - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
  3719. - (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
  3720. + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x*w,*d")
  3721. + (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x*w"))]
  3722. "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
  3723. && (register_operand (operands[0], QImode)
  3724. || register_operand (operands[1], QImode)
  3725. @@ -6072,7 +6592,7 @@
  3726.  
  3727. (define_insn "movqi_internal2"
  3728. [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
  3729. - (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
  3730. + (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x*w"))]
  3731. "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
  3732. && (register_operand (operands[0], QImode)
  3733. || register_operand (operands[1], QImode)
  3734. @@ -6289,12 +6809,13 @@
  3735. ;; This is volatile to make sure that the scheduler won't move any symbol_ref
  3736. ;; uses in front of it. All symbol_refs implicitly use the gp reg.
  3737.  
  3738. +;; FIXME: what is this for? needed for r5900 PIC?
  3739. (define_insn "loadgp"
  3740. [(set (reg:DI 28)
  3741. (unspec_volatile:DI [(match_operand:DI 0 "address_operand" "")
  3742. (match_operand:DI 1 "register_operand" "")] 2))
  3743. (clobber (reg:DI 1))]
  3744. - ""
  3745. + "!TARGET_MIPS5900"
  3746. "%[lui\\t$1,%%hi(%%neg(%%gp_rel(%a0)))\\n\\taddiu\\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\\n\\tdaddu\\t$gp,$1,%1%]"
  3747. [(set_attr "type" "move")
  3748. (set_attr "mode" "DI")
  3749. @@ -9568,7 +10089,7 @@
  3750. }")
  3751.  
  3752. ;; Trivial return. Make it look like a normal return insn as that
  3753. -;; allows jump optimizations to work better .
  3754. +;; allows jump optimizations to work better.
  3755. (define_insn "return"
  3756. [(return)]
  3757. "mips_can_use_return_insn ()"
  3758. @@ -9773,6 +10294,37 @@
  3759. (set_attr "mode" "none")
  3760. (set_attr "length" "8")])
  3761.  
  3762. +;;
  3763. +;; use jalr instead of jal
  3764. +;;
  3765. +(define_insn "call_indirect_internal"
  3766. + [ (unspec_volatile [
  3767. + (match_operand 0 "call_insn_operand" "ri")
  3768. + (match_operand 1 "" "i")
  3769. + (match_operand:SI 2 "register_operand" "=d") ] 30 )]
  3770. + ""
  3771. + "*
  3772. +{
  3773. + register rtx target = operands[0];
  3774. +
  3775. + if (GET_CODE (target) == SYMBOL_REF)
  3776. + {
  3777. + if (GET_MODE (target) == SImode)
  3778. + return \"la\\t%^,%0\\n\\tjalr\\t%2,%^\";
  3779. + else
  3780. + return \"dla\\t%^,%0\\n\\tjalr\\t%2,%^\";
  3781. + }
  3782. + else if (GET_CODE (target) == CONST_INT)
  3783. + return \"li\\t%^,%0\\n\\tjalr\\t%2,%^\";
  3784. + else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
  3785. + return \"move\\t%^,%0\\n\\tjalr\\t%2,%^\";
  3786. + else
  3787. + return \"jalr\\t%2,%0\";
  3788. +}"
  3789. + [(set_attr "type" "call")
  3790. + (set_attr "mode" "none")
  3791. + (set_attr "length" "8")])
  3792. +
  3793. (define_insn "call_internal1"
  3794. [(call (mem (match_operand 0 "call_insn_operand" "ri"))
  3795. (match_operand 1 "" "i"))
  3796. @@ -9805,6 +10357,8 @@
  3797. return \"li\\t%^,%0\\n\\tjal\\t%2,%^\";
  3798. else if (CONSTANT_ADDRESS_P (target))
  3799. {
  3800. + if (REGNO (operands[2]) == (31 + GP_REG_FIRST))
  3801. + return \"jal\\t%0\";
  3802. if (GET_MODE (target) == SImode)
  3803. return \"la\\t%^,%0\\n\\tjal\\t%2,%^\";
  3804. else
  3805. @@ -10013,6 +10567,8 @@
  3806. return \"li\\t%^,%1\\n\\tjal\\t%3,%^\";
  3807. else if (CONSTANT_ADDRESS_P (target))
  3808. {
  3809. + if (REGNO (operands[3]) == (31 + GP_REG_FIRST))
  3810. + return \"jal\\t%1\";
  3811. if (GET_MODE (target) == SImode)
  3812. return \"la\\t%^,%1\\n\\tjal\\t%3,%^\";
  3813. else
  3814. @@ -10148,6 +10704,8 @@
  3815. return \"li\\t%^,%1\\n\\tjal\\t%4,%^\";
  3816. else if (CONSTANT_ADDRESS_P (target))
  3817. {
  3818. + if (REGNO (operands[4]) == (31 + GP_REG_FIRST))
  3819. + return \"jal\\t%1\";
  3820. if (GET_MODE (target) == SImode)
  3821. return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
  3822. else
  3823. @@ -10205,6 +10763,15 @@
  3824. [(set_attr "type" "nop")
  3825. (set_attr "mode" "none")])
  3826.  
  3827. +;; Used by the r5900 loop lengthening code.
  3828. +
  3829. +(define_insn "nop_internal"
  3830. + [ (unspec_volatile [(const_int 0)] 31)]
  3831. + "TARGET_MIPS5900"
  3832. + "%(nop%)"
  3833. + [(set_attr "type" "nop")
  3834. + (set_attr "mode" "none")])
  3835. +
  3836. ;; The MIPS chip does not seem to require stack probes.
  3837. ;;
  3838. ;; (define_expand "probe"
  3839. @@ -10419,6 +10986,11 @@
  3840. "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
  3841. "
  3842. {
  3843. + /* XXX: Verify this */
  3844. + if (TARGET_MIPS5900
  3845. + && GET_MODE_CLASS (GET_MODE (branch_cmp[0])) == MODE_FLOAT)
  3846. + FAIL;
  3847. +
  3848. gen_conditional_move (operands);
  3849. DONE;
  3850. }")
  3851. @@ -10720,3 +11292,175 @@
  3852. [(set_attr "type" "arith")
  3853. (set_attr "mode" "DI")
  3854. (set_attr "length" "40")])
  3855. +
  3856. +;; r5900 MultiMedia Instructions (MMI)
  3857. +;; A lot of this code is based on the MMX implementation in i386.md. The main
  3858. +;; differences between MMX and MMI is that MMI supports 128-bit wide vector
  3859. +;; operations and MMI operates directly on the r5900 128-bit GPRs vs. needing
  3860. +;; a special set of MM-dedicated registers. Most of the instructions have the
  3861. +;; same mnemonics and perform similiar operations.
  3862. +
  3863. +;; Supported vector types
  3864. +;; 16 x 8 bits = V16QI
  3865. +;; 8 x 16 bits = V8HI
  3866. +;; 4 x 32 bits = V4SI and V4SF
  3867. +;; 2 x 64 bits = V2DI and V2SF
  3868. +;;
  3869. +
  3870. +;; MMI arithmetic
  3871. +;; TODO: Add the alternative where operand 1 == operand 2
  3872. +
  3873. +(define_insn "addv16qi3"
  3874. + [(set (match_operand:V16QI 0 "register_operand" "=d")
  3875. + (plus:V16QI (match_operand:V16QI 1 "register_operand" "d")
  3876. + (match_operand:V16QI 2 "register_operand" "d")))]
  3877. + "TARGET_MMI"
  3878. + "paddb\\t%0,%1,%2"
  3879. + [(set_attr "type" "mmi")])
  3880. +
  3881. +(define_insn "addv8hi3"
  3882. + [(set (match_operand:V8HI 0 "register_operand" "=d")
  3883. + (plus:V8HI (match_operand:V8HI 1 "register_operand" "d")
  3884. + (match_operand:V8HI 2 "register_operand" "d")))]
  3885. + "TARGET_MMI"
  3886. + "paddh\\t%0,%1,%2"
  3887. + [(set_attr "type" "mmi")])
  3888. +
  3889. +(define_insn "addv4si3"
  3890. + [(set (match_operand:V4SI 0 "register_operand" "=d")
  3891. + (plus:V4SI (match_operand:V4SI 1 "register_operand" "d")
  3892. + (match_operand:V4SI 2 "register_operand" "d")))]
  3893. + "TARGET_MMI"
  3894. + "paddw\\t%0,%1,%2"
  3895. + [(set_attr "type" "mmi")])
  3896. +
  3897. +;; Signed saturation
  3898. +
  3899. +(define_insn "ssaddv16qi3"
  3900. + [(set (match_operand:V16QI 0 "register_operand" "=d")
  3901. + (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "d")
  3902. + (match_operand:V16QI 2 "register_operand" "d")))]
  3903. + "TARGET_MMI"
  3904. + "paddsb\\t%0,%1,%2"
  3905. + [(set_attr "type" "mmi")])
  3906. +
  3907. +(define_insn "ssaddv8hi3"
  3908. + [(set (match_operand:V8HI 0 "register_operand" "=d")
  3909. + (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "d")
  3910. + (match_operand:V8HI 2 "register_operand" "d")))]
  3911. + "TARGET_MMI"
  3912. + "paddsh\\t%0,%1,%2"
  3913. + [(set_attr "type" "mmi")])
  3914. +
  3915. +(define_insn "ssaddv4si3"
  3916. + [(set (match_operand:V4SI 0 "register_operand" "=d")
  3917. + (ss_plus:V4SI (match_operand:V4SI 1 "register_operand" "d")
  3918. + (match_operand:V4SI 2 "register_operand" "d")))]
  3919. + "TARGET_MMI"
  3920. + "paddsw\\t%0,%1,%2"
  3921. + [(set_attr "type" "mmi")])
  3922. +
  3923. +;; Unsigned saturation
  3924. +
  3925. +(define_insn "usaddv16qi3"
  3926. + [(set (match_operand:V16QI 0 "register_operand" "=d")
  3927. + (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "d")
  3928. + (match_operand:V16QI 2 "register_operand" "d")))]
  3929. + "TARGET_MMI"
  3930. + "paddub\\t%0,%1,%2"
  3931. + [(set_attr "type" "mmi")])
  3932. +
  3933. +(define_insn "usaddv8hi3"
  3934. + [(set (match_operand:V8HI 0 "register_operand" "=d")
  3935. + (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "d")
  3936. + (match_operand:V8HI 2 "register_operand" "d")))]
  3937. + "TARGET_MMI"
  3938. + "padduh\\t%0,%1,%2"
  3939. + [(set_attr "type" "mmi")])
  3940. +
  3941. +(define_insn "usaddv4si3"
  3942. + [(set (match_operand:V4SI 0 "register_operand" "=d")
  3943. + (us_plus:V4SI (match_operand:V4SI 1 "register_operand" "d")
  3944. + (match_operand:V4SI 2 "register_operand" "d")))]
  3945. + "TARGET_MMI"
  3946. + "padduw\\t%0,%1,%2"
  3947. + [(set_attr "type" "mmi")])
  3948. +
  3949. +;; Subtraction
  3950. +
  3951. +(define_insn "subv16qi3"
  3952. + [(set (match_operand:V16QI 0 "register_operand" "=d")
  3953. + (minus:V16QI (match_operand:V16QI 1 "register_operand" "d")
  3954. + (match_operand:V16QI 2 "register_operand" "d")))]
  3955. + "TARGET_MMI"
  3956. + "psubb\\t%0,%1,%2"
  3957. + [(set_attr "type" "mmi")])
  3958. +
  3959. +(define_insn "subv8hi3"
  3960. + [(set (match_operand:V8HI 0 "register_operand" "=d")
  3961. + (minus:V8HI (match_operand:V8HI 1 "register_operand" "d")
  3962. + (match_operand:V8HI 2 "register_operand" "d")))]
  3963. + "TARGET_MMI"
  3964. + "psubh\\t%0,%1,%2"
  3965. + [(set_attr "type" "mmi")])
  3966. +
  3967. +(define_insn "subv4si3"
  3968. + [(set (match_operand:V4SI 0 "register_operand" "=d")
  3969. + (minus:V4SI (match_operand:V4SI 1 "register_operand" "d")
  3970. + (match_operand:V4SI 2 "register_operand" "d")))]
  3971. + "TARGET_MMI"
  3972. + "psubw\\t%0,%1,%2"
  3973. + [(set_attr "type" "mmi")])
  3974. +
  3975. +;; Signed saturation
  3976. +
  3977. +(define_insn "sssubv16qi3"
  3978. + [(set (match_operand:V16QI 0 "register_operand" "=d")
  3979. + (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "d")
  3980. + (match_operand:V16QI 2 "register_operand" "d")))]
  3981. + "TARGET_MMI"
  3982. + "psubsb\\t%0,%1,%2"
  3983. + [(set_attr "type" "mmi")])
  3984. +
  3985. +(define_insn "sssubv8hi3"
  3986. + [(set (match_operand:V8HI 0 "register_operand" "=d")
  3987. + (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "d")
  3988. + (match_operand:V8HI 2 "register_operand" "d")))]
  3989. + "TARGET_MMI"
  3990. + "psubsh\\t%0,%1,%2"
  3991. + [(set_attr "type" "mmi")])
  3992. +
  3993. +(define_insn "sssubv4si3"
  3994. + [(set (match_operand:V4SI 0 "register_operand" "=d")
  3995. + (ss_minus:V4SI (match_operand:V4SI 1 "register_operand" "d")
  3996. + (match_operand:V4SI 2 "register_operand" "d")))]
  3997. + "TARGET_MMI"
  3998. + "psubsw\\t%0,%1,%2"
  3999. + [(set_attr "type" "mmi")])
  4000. +
  4001. +;; Unsigned saturation
  4002. +
  4003. +(define_insn "ussubv16qi3"
  4004. + [(set (match_operand:V16QI 0 "register_operand" "=d")
  4005. + (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "d")
  4006. + (match_operand:V16QI 2 "register_operand" "d")))]
  4007. + "TARGET_MMI"
  4008. + "psubub\\t%0,%1,%2"
  4009. + [(set_attr "type" "mmi")])
  4010. +
  4011. +(define_insn "ussubv8hi3"
  4012. + [(set (match_operand:V8HI 0 "register_operand" "=d")
  4013. + (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "d")
  4014. + (match_operand:V8HI 2 "register_operand" "d")))]
  4015. + "TARGET_MMI"
  4016. + "psubuh\\t%0,%1,%2"
  4017. + [(set_attr "type" "mmi")])
  4018. +
  4019. +(define_insn "ussubv4si3"
  4020. + [(set (match_operand:V4SI 0 "register_operand" "=d")
  4021. + (us_minus:V4SI (match_operand:V4SI 1 "register_operand" "d")
  4022. + (match_operand:V4SI 2 "register_operand" "d")))]
  4023. + "TARGET_MMI"
  4024. + "psubuw\\t%0,%1,%2"
  4025. + [(set_attr "type" "mmi")])
  4026. +
  4027. diff -burN orig.gcc-3.2.3/gcc/config/mips/mips-protos.h gcc-3.2.3/gcc/config/mips/mips-protos.h
  4028. --- orig.gcc-3.2.3/gcc/config/mips/mips-protos.h 2002-03-24 04:13:16.000000000 -0400
  4029. +++ gcc-3.2.3/gcc/config/mips/mips-protos.h 2015-08-10 16:09:43 +0300
  4030. @@ -82,6 +82,7 @@
  4031. extern void mips_gen_conditional_trap PARAMS ((rtx *));
  4032. extern void mips_emit_fcc_reload PARAMS ((rtx, rtx, rtx));
  4033. extern void machine_dependent_reorg PARAMS ((rtx));
  4034. +extern void machine_dependent_reorg_final PARAMS ((rtx));
  4035. extern int mips_address_cost PARAMS ((rtx));
  4036. extern void mips_count_memory_refs PARAMS ((rtx, int));
  4037. extern HOST_WIDE_INT mips_debugger_offset PARAMS ((rtx, HOST_WIDE_INT));
  4038. diff -burN orig.gcc-3.2.3/gcc/config/mips/r5900.h gcc-3.2.3/gcc/config/mips/r5900.h
  4039. --- orig.gcc-3.2.3/gcc/config/mips/r5900.h 1969-12-31 20:00:00.000000000 -0400
  4040. +++ gcc-3.2.3/gcc/config/mips/r5900.h 2007-07-26 13:04:40.000000000 -0300
  4041. @@ -0,0 +1,285 @@
  4042. +/*
  4043. + * Target machine definitions for the Toshiba r5900.
  4044. + *
  4045. + * Copyright (c) 2003 M. R. Brown <mrbrown@0xd6.org>
  4046. + *
  4047. + * Based on the file elf5900.h, which originally bore
  4048. + * the copyright banner:
  4049. + *
  4050. + * Definitions of target machine for GNU compiler.
  4051. + * Toshiba r5900 little-endian
  4052. + * Copyright (c) 1995 Cygnus Support Inc.
  4053. + *
  4054. + * Also based on the PS2/Linux GCC port provided by SCEI and SCEA.
  4055. + *
  4056. + * Licensed under the terms of the GNU GPL version 2.
  4057. + */
  4058. +
  4059. +/* TODO: Add Linux support. */
  4060. +
  4061. +#include "mips/elf64.h"
  4062. +#include "mips/abi64.h"
  4063. +
  4064. +#define MIPS_CPU_STRING_DEFAULT "R5900"
  4065. +
  4066. +#undef MIPS_ABI_DEFAULT
  4067. +#define MIPS_ABI_DEFAULT ABI_EABI
  4068. +
  4069. +#undef MIPS_ISA_DEFAULT
  4070. +#define MIPS_ISA_DEFAULT 3
  4071. +
  4072. +#undef MACHINE_TYPE
  4073. +#define MACHINE_TYPE "(MIPSel R5900 ELF)"
  4074. +
  4075. +/*
  4076. + I started doing some macro fixes, but as we plan to use 3.4 soon I'm not risking changing stuff I'm not
  4077. + certain about.
  4078. +*/
  4079. +/*
  4080. +#define USE_MACRO_FIXES
  4081. +*/
  4082. +
  4083. +/*
  4084. + gcc-3.0.3-ps2linux has additional min.s and max.s floating point insns. These should be incorporate into mips.md.
  4085. +*/
  4086. +
  4087. +#define FILL_BDSLOT_WITH_NOP
  4088. +
  4089. +/*
  4090. + * Use Gas, target r5900, -msingle-float, 64-bit CPU and longs, split-addr (avoids la insn emits), -mmmi
  4091. + */
  4092. +#undef TARGET_DEFAULT
  4093. +#define TARGET_DEFAULT ( MASK_GAS | MASK_SINGLE_FLOAT | MASK_64BIT \
  4094. + | MASK_LONG64 | MASK_MMI | MASK_VUMM | MASK_SPLIT_ADDR )
  4095. +
  4096. +/*
  4097. + * Even though we're a 64-bit processor, we only support a 32-bit address
  4098. + * space.
  4099. + */
  4100. +#undef Pmode
  4101. +#define Pmode SImode
  4102. +
  4103. +/* 128-bit alignment options */
  4104. +#define DEFAULT_MIPS_ALIGNMENT 128
  4105. +
  4106. +/* TODO: need to make this variable */
  4107. +#undef BIGGEST_ALIGNMENT
  4108. +#define BIGGEST_ALIGNMENT DEFAULT_MIPS_ALIGNMENT
  4109. +
  4110. +#undef SUBTARGET_TARGET_OPTIONS
  4111. +#define SUBTARGET_TARGET_OPTIONS \
  4112. + { "use-128", &mips_use_128_string, \
  4113. + N_("Use 128-bit operations")}, \
  4114. + { "align128", &mips_align128_string, \
  4115. + N_("Use 128-bit alignment")}, \
  4116. + { "no-align128", &mips_no_align128_string, \
  4117. + N_("Don't use 128-bit alignment")}, \
  4118. + { "abi=", &mips_abi_string, \
  4119. + N_("Speciy ABI to use")},
  4120. +
  4121. +/* Stack alignment */
  4122. +#undef STACK_BOUNDARY
  4123. +#define STACK_BOUNDARY \
  4124. + ((mips_abi == ABI_32 || mips_abi == ABI_O64 || (mips_abi == ABI_EABI \
  4125. + && !TARGET_MIPS5900)) \
  4126. + ? 64 : 128)
  4127. +
  4128. +#undef MIPS_STACK_ALIGN
  4129. +#define MIPS_STACK_ALIGN(LOC) \
  4130. + (((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
  4131. + && mips_alignment != 128 ) \
  4132. + ? ((LOC) + 7) & ~7 \
  4133. + : ((LOC) + 15) & ~15)
  4134. +
  4135. +#define PREFERRED_STACK_BOUNDARY \
  4136. +(mips_alignment == 128 ? 128 : \
  4137. + ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI ) \
  4138. + ? 64 : 128))
  4139. +
  4140. +/* TODO: Find a way to specify default alignments for functions, jumps,
  4141. + and loops. These used to be machine dependant, but now live as -f
  4142. + parameters. */
  4143. +
  4144. +/* prefer .p2align rather than .align (gas assumed) */
  4145. +#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
  4146. + if ((LOG)!=0) \
  4147. + if ((MAX_SKIP)==0) fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
  4148. + else fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP))
  4149. +
  4150. +/* How to output a quadword for the r5900. */
  4151. +#define ASM_OUTPUT_QUADRUPLE_INT(STREAM,VALUE) \
  4152. +do { \
  4153. + if (TARGET_64BIT) \
  4154. + { \
  4155. + fprintf (STREAM, "\t.octa\t"); \
  4156. + if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
  4157. + /* We can't use 'X' for negative numbers, because then we won't \
  4158. + get the right value for the upper 32 bits. */ \
  4159. + output_addr_const (STREAM, VALUE); \
  4160. + else \
  4161. + /* We must use 'X', because otherwise LONG_MIN will print as \
  4162. + a number that the Irix 6 assembler won't accept. */ \
  4163. + print_operand (STREAM, VALUE, 'X'); \
  4164. + fprintf (STREAM, "\n"); \
  4165. + } \
  4166. + else \
  4167. + { \
  4168. + assemble_integer (operand_subword ((VALUE), 0, 0, TImode), \
  4169. + UNITS_PER_WORD, 1); \
  4170. + assemble_integer (operand_subword ((VALUE), 1, 0, TImode), \
  4171. + UNITS_PER_WORD, 1); \
  4172. + } \
  4173. +} while (0)
  4174. +
  4175. +
  4176. +#undef CPP_PREDEFINES
  4177. +#define CPP_PREDEFINES "\
  4178. +-D__ELF__ \
  4179. +-Dmips -D_mips -D__mips -D__mips__ \
  4180. +%{!miop: -DR5900 -D_R5900 -D__R5900 -D_EE } \
  4181. +%{miop: -DR3000 -D_3000 -D__3000 } \
  4182. +-DMIPSEL -D_MIPSEL -D__MIPSEL -D__MIPSEL__ \
  4183. +-Acpu(mips) -Amachine(mips) \
  4184. +"
  4185. +
  4186. +/* Default to 32-bit ints and 64-bit longs. */
  4187. +#undef SUBTARGET_CPP_SIZE_SPEC
  4188. +#define SUBTARGET_CPP_SIZE_SPEC "\
  4189. +%{mgp64: -D_MIPS_SZPTR=32 } \
  4190. +%{!mgp64: -D_MIPS_SZPTR=32 } \
  4191. +\
  4192. +%{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int \
  4193. + -D__SSIZE_TYPE__=long\\ int \
  4194. + -D__PTRDIFF_TYPE__=long\\ int \
  4195. + -D_MIPS_SZLONG=64} \
  4196. +\
  4197. +%{mint64:-D_MIPS_SZINT=64 \
  4198. + %{!mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int \
  4199. + -D__SSIZE_TYPE__=long\\ int \
  4200. + -D__PTRDIFF_TYPE__=long\\ int \
  4201. + -D_MIPS_SZLONG=64}} \
  4202. +\
  4203. +%{!mint64:-D_MIPS_SZINT=32 \
  4204. + %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int \
  4205. + -D__SSIZE_TYPE__=int \
  4206. + -D__PTRDIFF_TYPE__=int \
  4207. + -D_MIPS_SZLONG=64}} \
  4208. +"
  4209. +
  4210. +#undef SUBTARGET_CPP_SPEC
  4211. +#define SUBTARGET_CPP_SPEC "\
  4212. +%{mfp32: -D_MIPS_FPSET=16}%{!mfp32: -D_MIPS_FPSET=32} \
  4213. +%{mips1: -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
  4214. +%{mips2: -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS2} \
  4215. +%{mips3: -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS3 -UR3000 -U_R3000} \
  4216. +%{mips4: -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS4 -UR3000 -U_R3000} \
  4217. +%{!mips*: -U__mips -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS3 -D__mips=3 -D__mips64} \
  4218. +%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}} \
  4219. +%{!msoft-float: %{!mdouble-float : -D__mips_single_float}} \
  4220. +%{-D__HAVE_FPU__ } \
  4221. +%{posix: -D_POSIX_SOURCE} \
  4222. +%{.cc: -D__LANGUAGE_C_PLUS_PLUS__ %{!ansi:-DLANGUAGE_C_PLUS_PLUS}} \
  4223. +%{.cxx: -D__LANGUAGE_C_PLUS_PLUS__ %{!ansi:-DLANGUAGE_C_PLUS_PLUS}} \
  4224. +%{.C: -D__LANGUAGE_C_PLUS_PLUS__ %{!ansi:-DLANGUAGE_C_PLUS_PLUS}} \
  4225. +%{.m: -D__LANGUAGE_OBJECTIVE_C__ %{!ansi:-DLANGUAGE_OBJECTIVE_C}} \
  4226. +%{.S: -D__LANGUAGE_ASSEMBLY__ %{!ansi:-DLANGUAGE_ASSEMBLY}} \
  4227. +%{.s: -D__LANGUAGE_ASSEMBLY__ %{!ansi:-DLANGUAGE_ASSEMBLY}} \
  4228. +%{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C__ %{!ansi:-DLANGUAGE_C}}}}}} } \
  4229. +%{ansi:-Uunix -Ulinux -Umips -UR3000 -UMIPSEB -UMIPSEL} \
  4230. +%{ffast-math: -D__FAST_MATH__} \
  4231. + "
  4232. +
  4233. +/* The GNU C++ standard library requires that these macros be defined. */
  4234. +#undef CPLUSPLUS_CPP_SPEC
  4235. +#define CPLUSPLUS_CPP_SPEC "\
  4236. +-D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
  4237. +-D_GNU_SOURCE %(cpp) \
  4238. + "
  4239. +
  4240. +#undef SUBTARGET_ASM_SPEC
  4241. +#define SUBTARGET_ASM_SPEC "\
  4242. +%{!march*: %{!miop: -mwarn-short-loop -march=r5900} %{miop: -march=r3000}} \
  4243. +%{!mips*: %{!miop: -mips3 %{!mfp*: -mfp32} %{!mgp*: -mgp64}} %{miop: -mips1 %{!mfp*: -mfp32} %{!mgp*: -mgp32}}} \
  4244. +%{!mabi*: %{!miop: -mabi=eabi}} \
  4245. +%{!mdouble-float: -msingle-float} \
  4246. + "
  4247. +
  4248. +/*
  4249. + * We want to include alignment directives for the r5900 to ensure that
  4250. + * TImode values are properly aligned. It would be best to do this in
  4251. + * mips.h, but it's unclear if all mips assemblers can handle alignments
  4252. + * for local common/bss objects.
  4253. + */
  4254. +#undef ASM_OUTPUT_LOCAL
  4255. +
  4256. +/*
  4257. + * This says how to output an assembler line to define a global common symbol
  4258. + * with size SIZE (in bytes) and alignment ALIGN (in bits).
  4259. + */
  4260. +
  4261. +#undef ASM_OUTPUT_ALIGNED_COMMON
  4262. +#define ASM_OUTPUT_ALIGNED_COMMON(STREAM, NAME, SIZE, ALIGN) \
  4263. +do \
  4264. +{ \
  4265. + mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u,", (SIZE)); \
  4266. + fprintf ((STREAM), "%d\n", ((ALIGN) / BITS_PER_UNIT)); \
  4267. +} \
  4268. +while (0)
  4269. +
  4270. +#define POPSECTION_ASM_OP "\t.previous"
  4271. +#define BSS_SECTION_ASM_OP "\t.section\t.bss"
  4272. +#define SBSS_SECTION_ASM_OP "\t.section\t.sbss"
  4273. +#undef ASM_OUTPUT_ALIGNED_LOCAL
  4274. +#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
  4275. +do \
  4276. + { \
  4277. + if ((SIZE) > 0 && (SIZE) <= mips_section_threshold) \
  4278. + fprintf (STREAM, "%s\n", SBSS_SECTION_ASM_OP); \
  4279. + else \
  4280. + fprintf (STREAM, "%s\n", BSS_SECTION_ASM_OP); \
  4281. + mips_declare_object (STREAM, NAME, "", ":\n", 0); \
  4282. + ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
  4283. + ASM_OUTPUT_SKIP (STREAM, SIZE); \
  4284. + fprintf (STREAM, "%s\n", POPSECTION_ASM_OP); \
  4285. + } \
  4286. +while (0)
  4287. +
  4288. +/*
  4289. + * Avoid returning unaligned structures > 64bits, but <= 128bits wide
  4290. + * in registers.
  4291. + *
  4292. + * This avoids a bad interaction between the code to return BLKmode
  4293. + * structures in registers and the wider than word_mode registers
  4294. + * found on the r5900.
  4295. + *
  4296. + * This does not effect returning an aligned 128bit value in a register,
  4297. + * which should work.
  4298. + */
  4299. +
  4300. +#undef RETURN_IN_MEMORY
  4301. +#define RETURN_IN_MEMORY(TYPE) \
  4302. + ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
  4303. + ? TYPE_MODE (TYPE) == BLKmode \
  4304. + : (mips_abi == ABI_EABI && TYPE_MODE (TYPE) == BLKmode \
  4305. + ? (int_size_in_bytes (TYPE) > UNITS_PER_WORD) \
  4306. + : (int_size_in_bytes (TYPE) \
  4307. + > (mips_abi == ABI_EABI ? 2 * UNITS_PER_WORD : 16))))
  4308. +
  4309. +#define EH_FRAME_IN_DATA_SECTION 1
  4310. +
  4311. +/*
  4312. + * This patch is ugly. But it hopefully will put an end to that
  4313. + * 128-bits alignment madness.
  4314. + */
  4315. +
  4316. +#undef CONSTANT_ALIGNMENT
  4317. +#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
  4318. + ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
  4319. + && (ALIGN) < (mips_use_128 ? 128 : 64) ? (mips_use_128 ? 128 : 64) : (ALIGN))
  4320. +
  4321. +#undef DATA_ALIGNMENT
  4322. +#define DATA_ALIGNMENT(TYPE, ALIGN) \
  4323. + ((((ALIGN) < (mips_use_128 ? 128 : 64)) \
  4324. + && (TREE_CODE (TYPE) == ARRAY_TYPE \
  4325. + || TREE_CODE (TYPE) == UNION_TYPE \
  4326. + || TREE_CODE (TYPE) == RECORD_TYPE)) ? (mips_use_128 ? 128 : 64) : (ALIGN))
  4327. diff -burN orig.gcc-3.2.3/gcc/config/mips/t-irx gcc-3.2.3/gcc/config/mips/t-irx
  4328. --- orig.gcc-3.2.3/gcc/config/mips/t-irx 1969-12-31 20:00:00.000000000 -0400
  4329. +++ gcc-3.2.3/gcc/config/mips/t-irx 2007-07-26 13:04:40.000000000 -0300
  4330. @@ -0,0 +1,77 @@
  4331. +CONFIG2_H = $(srcdir)/config/mips/ecoff.h
  4332. +
  4333. +# Don't run fixproto
  4334. +STMP_FIXPROTO =
  4335. +
  4336. +# Suppress building libgcc1.a, since the MIPS compiler port is complete
  4337. +# and does not need anything from libgcc1.a.
  4338. +LIBGCC1 =
  4339. +CROSS_LIBGCC1 =
  4340. +
  4341. +# We must build libgcc2.a with -G 0, in case the user wants to link
  4342. +# without the $gp register.
  4343. +TARGET_LIBGCC2_CFLAGS = -G 0
  4344. +
  4345. +# We want fine grained libraries, so use the new code to build the
  4346. +# floating point emulation libraries.
  4347. +FPBIT = fp-bit.c
  4348. +DPBIT = dp-bit.c
  4349. +
  4350. +dp-bit.c: $(srcdir)/config/fp-bit.c
  4351. + echo '#ifdef __MIPSEL__' > dp-bit.c
  4352. + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
  4353. + echo '#endif' >> dp-bit.c
  4354. + echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
  4355. + cat $(srcdir)/config/fp-bit.c >> dp-bit.c
  4356. +
  4357. +fp-bit.c: $(srcdir)/config/fp-bit.c
  4358. + echo '#define FLOAT' > fp-bit.c
  4359. + echo '#ifdef __MIPSEL__' >> fp-bit.c
  4360. + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
  4361. + echo '#endif' >> fp-bit.c
  4362. + echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
  4363. + cat $(srcdir)/config/fp-bit.c >> fp-bit.c
  4364. +
  4365. +# Build the libraries for both hard and soft floating point
  4366. +
  4367. +MULTILIB_OPTIONS =
  4368. +MULTILIB_DIRNAMES =
  4369. +MULTILIB_MATCHES =
  4370. +
  4371. +# Library members defined in libgcc2.c.
  4372. +# LIB2FUNCS = _muldi3 _divdi3 _moddi3 _udivdi3 _umoddi3 _negdi2 \
  4373. +# _lshrdi3 _ashldi3 _ashrdi3 _ffsdi2 \
  4374. +# _udiv_w_sdiv _udivmoddi4 _cmpdi2 _ucmpdi2 \
  4375. +# __gcc_bcmp _varargs __dummy
  4376. +
  4377. +
  4378. +# Add additional dependencies to recompile selected modules whenever the
  4379. +# tm.h file changes. The files compiled are:
  4380. +#
  4381. +# gcc.c (*_SPEC changes)
  4382. +# toplev.c (new switches + assembly output changes)
  4383. +# sdbout.c (debug format changes)
  4384. +# dbxout.c (debug format changes)
  4385. +# dwarfout.c (debug format changes)
  4386. +# final.c (assembly output changes)
  4387. +# varasm.c (assembly output changes)
  4388. +# cse.c (cost functions)
  4389. +# insn-output.c (possible ifdef changes in tm.h)
  4390. +# regclass.c (fixed/call used register changes)
  4391. +# explow.c (GO_IF_LEGITIMATE_ADDRESS)
  4392. +# recog.c (GO_IF_LEGITIMATE_ADDRESS)
  4393. +# reload.c (GO_IF_LEGITIMATE_ADDRESS)
  4394. +
  4395. +gcc.o: $(CONFIG2_H)
  4396. +toplev.o: $(CONFIG2_H)
  4397. +sdbout.o: $(CONFIG2_H)
  4398. +dbxout.o: $(CONFIG2_H)
  4399. +dwarfout.o: $(CONFIG2_H)
  4400. +final.o: $(CONFIG2_H)
  4401. +varasm.o: $(CONFIG2_H)
  4402. +cse.o: $(CONFIG2_H)
  4403. +insn-output.o: $(CONFIG2_H)
  4404. +regclass.o: $(CONFIG2_H)
  4405. +explow.o: $(CONFIG2_H)
  4406. +recog.o: $(CONFIG2_H)
  4407. +reload.o: $(CONFIG2_H)
  4408. diff -burN orig.gcc-3.2.3/gcc/config/mips/t-r5900 gcc-3.2.3/gcc/config/mips/t-r5900
  4409. --- orig.gcc-3.2.3/gcc/config/mips/t-r5900 1969-12-31 20:00:00.000000000 -0400
  4410. +++ gcc-3.2.3/gcc/config/mips/t-r5900 2007-07-26 13:04:40.000000000 -0300
  4411. @@ -0,0 +1,56 @@
  4412. +# Suppress building libgcc1.a, since the MIPS compiler port is complete
  4413. +# and does not need anything from libgcc1.a.
  4414. +LIBGCC1 =
  4415. +CROSS_LIBGCC1 =
  4416. +
  4417. +# We must build libgcc2.a with -G 0, in case the user wants to link
  4418. +# without the $gp register.
  4419. +TARGET_LIBGCC2_CFLAGS = -G 0
  4420. +
  4421. +# We want fine grained libraries, so use the new code to build the
  4422. +# floating point emulation libraries.
  4423. +FPBIT = fp-bit.c
  4424. +
  4425. +fp-bit.c: $(srcdir)/config/fp-bit.c
  4426. + echo '#define FLOAT' > fp-bit.c
  4427. + echo '#ifdef __MIPSEL__' >> fp-bit.c
  4428. + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
  4429. + echo '#endif' >> fp-bit.c
  4430. + echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
  4431. + cat $(srcdir)/config/fp-bit.c >> fp-bit.c
  4432. +
  4433. +# To reenable the double precision emulation code uncomment the next line and
  4434. +# the 6 lines that follow it.
  4435. +DPBIT = dp-bit.c
  4436. +
  4437. +dp-bit.c: $(srcdir)/config/fp-bit.c
  4438. + echo '#ifdef __MIPSEL__' > dp-bit.c
  4439. + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
  4440. + echo '#endif' >> dp-bit.c
  4441. + echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
  4442. + cat $(srcdir)/config/fp-bit.c >> dp-bit.c
  4443. +
  4444. +# Don't let CTOR_LIST end up in sdata section.
  4445. +CRTSTUFF_T_CFLAGS = -G 0
  4446. +
  4447. +# Assemble startup files.
  4448. +$(T)crti.o: $(srcdir)/config/mips/crti5900.asm $(GCC_PASSES)
  4449. + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
  4450. + -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti5900.asm
  4451. +
  4452. +$(T)crtn.o: $(srcdir)/config/mips/crtn5900.asm $(GCC_PASSES)
  4453. + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
  4454. + -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn5900.asm
  4455. +
  4456. +MULTILIB_OPTIONS =
  4457. +MULTILIB_DIRNAMES =
  4458. +EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
  4459. +
  4460. +#
  4461. +# TImode runtime support
  4462. +#
  4463. +LIBGCC_TIMODE_SRC = $(srcdir)/config/mips/libgcc2-timode.c
  4464. +TIMODE_FUNCS_LIST = _ashlti3 _ashrti3 _cmpti2 _divti3 _ffsti2 _fixdfti _fixunsdfti \
  4465. + _floattidf _floattisf _lshrti3 _modti3 _multi3 _negti2 _ucmpti2 _udivti3 _umodti3
  4466. +
  4467. +LIB2FUNCS_TI = $(TIMODE_FUNCS_LIST)
  4468. diff -burN orig.gcc-3.2.3/gcc/config.gcc gcc-3.2.3/gcc/config.gcc
  4469. --- orig.gcc-3.2.3/gcc/config.gcc 2003-01-30 10:03:42.000000000 -0400
  4470. +++ gcc-3.2.3/gcc/config.gcc 2007-07-26 13:04:40.000000000 -0300
  4471. @@ -1553,6 +1553,10 @@
  4472. *minwg32msv* | *mingw32*)
  4473. ;;
  4474. esac
  4475. + if test x$pass1done = xyes && test x$pass2done = x
  4476. + then
  4477. + host_to_target_tmake_file=i386/t-mingw32
  4478. + fi
  4479. ;;
  4480. i[34567]86-*-uwin*)
  4481. tm_file=i386/uwin.h
  4482. @@ -2387,6 +2391,13 @@
  4483. esac
  4484. tmake_file="t-slibgcc-elf-ver t-linux mips/t-linux"
  4485. extra_parts="crtbegin.o crtbeginS.o crtbeginT.o crtend.o crtendS.o"
  4486. + case $machine in
  4487. + mips*r5900*-*) # Linux for r5900 (EE)
  4488. + tm_file="$tm_file mips/r5900.h"
  4489. + tmake_file="$tmake_file t-r5900"
  4490. + extra_headers="core-mmi.h core-vumm.h"
  4491. + ;;
  4492. + esac
  4493. gnu_ld=yes
  4494. gas=yes
  4495. ;;
  4496. @@ -2583,6 +2594,24 @@
  4497. use_collect2=yes
  4498. fi
  4499. ;;
  4500. +mips*r5900*-*-elf*) # MIPS r5900 ELF, either endian
  4501. + tm_file="dbxelf.h elfos.h mips/r5900.h"
  4502. + tmake_file=mips/t-r5900
  4503. + case $machine in
  4504. + mips*el-*)
  4505. + tm_file="mips/little.h $tm_file"
  4506. + ;;
  4507. + esac
  4508. + gnu_ld=yes
  4509. + gas=yes
  4510. + extra_headers="core-mmi.h core-vumm.h"
  4511. + ;;
  4512. +mipsel-*-irx)
  4513. + tm_file="mips/elfl.h libgloss.h"
  4514. + tmake_file=mips/t-irx
  4515. + target_cpu_default="MASK_GAS|MASK_SOFT_FLOAT"
  4516. + fixincludes=Makefile.in
  4517. + ;;
  4518. mipsel-*-ecoff*)
  4519. tm_file=mips/ecoffl.h
  4520. if test x$stabs = xyes; then
  4521. @@ -3673,5 +3702,8 @@
  4522. host_extra_objs=$extra_host_objs
  4523. host_exeext=$exeext
  4524. pass2done=yes
  4525. + else
  4526. + tmake_file="$tmake_file $host_to_target_tmake_file"
  4527. fi
  4528. fi
  4529. +
  4530. diff -burN orig.gcc-3.2.3/gcc/cp/decl.c gcc-3.2.3/gcc/cp/decl.c
  4531. --- orig.gcc-3.2.3/gcc/cp/decl.c 2003-01-21 15:00:27.000000000 -0400
  4532. +++ gcc-3.2.3/gcc/cp/decl.c 2015-08-10 16:06:57 +0300
  4533. @@ -458,6 +458,10 @@
  4534. ? cp_function_chain->bindings \
  4535. : scope_chain->bindings)
  4536.  
  4537. +#define set_current_binding_level(x) \
  4538. + if(cfun && cp_function_chain->bindings) { cp_function_chain->bindings = (x); } \
  4539. + else { scope_chain->bindings = (x); }
  4540. +
  4541. /* The binding level of the current class, if any. */
  4542.  
  4543. #define class_binding_level scope_chain->class_bindings
  4544. @@ -507,7 +511,7 @@
  4545. are active. */
  4546. memset ((char*) newlevel, 0, sizeof (struct binding_level));
  4547. newlevel->level_chain = current_binding_level;
  4548. - current_binding_level = newlevel;
  4549. + set_current_binding_level(newlevel);
  4550. newlevel->tag_transparent = tag_transparent;
  4551. newlevel->more_cleanups_ok = 1;
  4552.  
  4553. @@ -563,7 +567,7 @@
  4554. #endif /* defined(DEBUG_CP_BINDING_LEVELS) */
  4555. {
  4556. register struct binding_level *level = current_binding_level;
  4557. - current_binding_level = current_binding_level->level_chain;
  4558. + set_current_binding_level(current_binding_level->level_chain);
  4559. level->level_chain = free_binding_level;
  4560. #if 0 /* defined(DEBUG_CP_BINDING_LEVELS) */
  4561. if (level->binding_depth != binding_depth)
  4562. @@ -578,7 +582,9 @@
  4563. suspend_binding_level ()
  4564. {
  4565. if (class_binding_level)
  4566. - current_binding_level = class_binding_level;
  4567. + {
  4568. + set_current_binding_level(class_binding_level);
  4569. + }
  4570.  
  4571. if (global_binding_level)
  4572. {
  4573. @@ -600,7 +606,7 @@
  4574. }
  4575. is_class_level = 0;
  4576. #endif /* defined(DEBUG_CP_BINDING_LEVELS) */
  4577. - current_binding_level = current_binding_level->level_chain;
  4578. + set_current_binding_level(current_binding_level->level_chain);
  4579. find_class_binding_level ();
  4580. }
  4581.  
  4582. @@ -613,7 +619,7 @@
  4583. my_friendly_assert(!class_binding_level, 386);
  4584. /* Also, resuming a non-directly nested namespace is a no-no. */
  4585. my_friendly_assert(b->level_chain == current_binding_level, 386);
  4586. - current_binding_level = b;
  4587. + set_current_binding_level(b);
  4588. #if defined(DEBUG_CP_BINDING_LEVELS)
  4589. b->binding_depth = binding_depth;
  4590. indent ();
  4591. @@ -4291,9 +4297,9 @@
  4592. else
  4593. {
  4594. b = current_binding_level;
  4595. - current_binding_level = level;
  4596. + set_current_binding_level(level);
  4597. x = pushdecl (x);
  4598. - current_binding_level = b;
  4599. + set_current_binding_level(b);
  4600. }
  4601. current_function_decl = function_decl;
  4602. return x;
  4603. @@ -4540,14 +4546,14 @@
  4604. return NULL_TREE;
  4605.  
  4606. ancestor = namespace_ancestor (current_decl_namespace (), used);
  4607. - ud = current_binding_level->using_directives;
  4608. - ud = tree_cons (used, ancestor, ud);
  4609. - current_binding_level->using_directives = ud;
  4610.  
  4611. /* Recursively add all namespaces used. */
  4612. for (iter = DECL_NAMESPACE_USING (used); iter; iter = TREE_CHAIN (iter))
  4613. push_using_directive (TREE_PURPOSE (iter));
  4614.  
  4615. + ud = current_binding_level->using_directives;
  4616. + ud = tree_cons (used, ancestor, ud);
  4617. + current_binding_level->using_directives = ud;
  4618. return ud;
  4619. }
  4620.  
  4621. @@ -6538,7 +6544,7 @@
  4622. current_lang_name = lang_name_c;
  4623.  
  4624. current_function_decl = NULL_TREE;
  4625. - current_binding_level = NULL_BINDING_LEVEL;
  4626. + set_current_binding_level(NULL_BINDING_LEVEL);
  4627. free_binding_level = NULL_BINDING_LEVEL;
  4628.  
  4629. build_common_tree_nodes (flag_signed_char);
  4630. @@ -10124,10 +10130,10 @@
  4631. if (decl_context == NORMAL && !toplevel_bindings_p ())
  4632. {
  4633. struct binding_level *b = current_binding_level;
  4634. - current_binding_level = b->level_chain;
  4635. + set_current_binding_level(b->level_chain);
  4636. if (current_binding_level != 0 && toplevel_bindings_p ())
  4637. decl_context = PARM;
  4638. - current_binding_level = b;
  4639. + set_current_binding_level(b);
  4640. }
  4641.  
  4642. if (name == NULL)
  4643. @@ -13757,7 +13763,7 @@
  4644. FIXME factor out the non-RTL stuff. */
  4645. bl = current_binding_level;
  4646. init_function_start (decl1, input_filename, lineno);
  4647. - current_binding_level = bl;
  4648. + set_current_binding_level(bl);
  4649.  
  4650. /* Even though we're inside a function body, we still don't want to
  4651. call expand_expr to calculate the size of a variable-sized array.
  4652. @@ -14309,20 +14315,11 @@
  4653. if (current_function_return_value)
  4654. {
  4655. tree r = current_function_return_value;
  4656. - tree outer;
  4657. -
  4658. - if (r != error_mark_node
  4659. /* This is only worth doing for fns that return in memory--and
  4660. simpler, since we don't have to worry about promoted modes. */
  4661. - && aggregate_value_p (TREE_TYPE (TREE_TYPE (fndecl)))
  4662. - /* Only allow this for variables declared in the outer scope of
  4663. - the function so we know that their lifetime always ends with a
  4664. - return; see g++.dg/opt/nrv6.C. We could be more flexible if
  4665. - we were to do this optimization in tree-ssa. */
  4666. - && (outer = BLOCK_SUBBLOCKS (DECL_INITIAL (fndecl)),
  4667. - chain_member (r, BLOCK_VARS (outer))))
  4668. + if (r != error_mark_node
  4669. + && aggregate_value_p (TREE_TYPE (TREE_TYPE (fndecl))))
  4670. {
  4671. -
  4672. DECL_ALIGN (r) = DECL_ALIGN (DECL_RESULT (fndecl));
  4673. walk_tree_without_duplicates (&DECL_SAVED_TREE (fndecl),
  4674. nullify_returns_r, r);
  4675. diff -burN orig.gcc-3.2.3/gcc/fixinc/gnu-regex.c gcc-3.2.3/gcc/fixinc/gnu-regex.c
  4676. --- orig.gcc-3.2.3/gcc/fixinc/gnu-regex.c 2002-02-26 20:23:56.000000000 -0400
  4677. +++ gcc-3.2.3/gcc/fixinc/gnu-regex.c 2007-07-26 13:04:40.000000000 -0300
  4678. @@ -26,6 +26,9 @@
  4679. # include <config.h>
  4680. #endif
  4681.  
  4682. +/* XXX :: Should find the correct way for other platforms that have mempcpy. this is a cygwin hack! */
  4683. +#undef HAVE_MEMPCPY
  4684. +
  4685. /* GCC LOCAL: we don't need NLS here. */
  4686. #undef ENABLE_NLS
  4687. /* GCC LOCAL: to handle defining alloca. */
  4688. diff -burN orig.gcc-3.2.3/gcc/fixinc/mkfixinc.sh gcc-3.2.3/gcc/fixinc/mkfixinc.sh
  4689. --- orig.gcc-3.2.3/gcc/fixinc/mkfixinc.sh 2002-01-05 00:06:51.000000000 -0400
  4690. +++ gcc-3.2.3/gcc/fixinc/mkfixinc.sh 2007-07-26 13:04:40.000000000 -0300
  4691. @@ -80,6 +80,8 @@
  4692. i?86-*-mingw32* | \
  4693. i?86-*-uwin* | \
  4694. mips-sgi-irix5cross64 | \
  4695. + mips64r5900el-scei-elf | \
  4696. + mipsel-scei-irx | \
  4697. powerpc-*-eabiaix* | \
  4698. powerpc-*-eabisim* | \
  4699. powerpc-*-eabi* | \
  4700. diff -burN orig.gcc-3.2.3/gcc/glimits.h gcc-3.2.3/gcc/glimits.h
  4701. --- orig.gcc-3.2.3/gcc/glimits.h 2001-08-13 21:53:23.000000000 -0300
  4702. +++ gcc-3.2.3/gcc/glimits.h 2007-07-26 13:04:40.000000000 -0300
  4703. @@ -67,11 +67,11 @@
  4704. /* Minimum and maximum values a `signed long int' can hold.
  4705. (Same as `int'). */
  4706. #ifndef __LONG_MAX__
  4707. -#if defined (__alpha__) || (defined (__sparc__) && defined(__arch64__)) || defined (__sparcv9)
  4708. +#if defined (__alpha__) || (defined (__sparc__) && defined(__arch64__)) || defined (__sparcv9) || defined (__R5900)
  4709. #define __LONG_MAX__ 9223372036854775807L
  4710. #else
  4711. #define __LONG_MAX__ 2147483647L
  4712. -#endif /* __alpha__ || sparc64 */
  4713. +#endif /* __alpha__ || sparc64 || R5900 */
  4714. #endif
  4715. #undef LONG_MIN
  4716. #define LONG_MIN (-LONG_MAX-1)
  4717. diff -burN orig.gcc-3.2.3/gcc/integrate.c gcc-3.2.3/gcc/integrate.c
  4718. --- orig.gcc-3.2.3/gcc/integrate.c 2003-02-03 16:56:29.000000000 -0400
  4719. +++ gcc-3.2.3/gcc/integrate.c 2007-07-26 13:04:40.000000000 -0300
  4720. @@ -358,12 +358,18 @@
  4721. /* Copy the declaration. */
  4722. if (TREE_CODE (decl) == PARM_DECL || TREE_CODE (decl) == RESULT_DECL)
  4723. {
  4724. + tree type;
  4725. + type = TREE_TYPE(decl);
  4726. +
  4727. /* For a parameter, we must make an equivalent VAR_DECL, not a
  4728. new PARM_DECL. */
  4729. copy = build_decl (VAR_DECL, DECL_NAME (decl), TREE_TYPE (decl));
  4730. TREE_ADDRESSABLE (copy) = TREE_ADDRESSABLE (decl);
  4731. TREE_READONLY (copy) = TREE_READONLY (decl);
  4732. TREE_THIS_VOLATILE (copy) = TREE_THIS_VOLATILE (decl);
  4733. +
  4734. + if (TYPE_RESTRICT(type))
  4735. + DECL_POINTER_ALIAS_SET (copy) = -2;
  4736. }
  4737. else
  4738. {
  4739. diff -burN orig.gcc-3.2.3/gcc/libgcc2-timode.c gcc-3.2.3/gcc/libgcc2-timode.c
  4740. --- orig.gcc-3.2.3/gcc/libgcc2-timode.c 1969-12-31 20:00:00.000000000 -0400
  4741. +++ gcc-3.2.3/gcc/libgcc2-timode.c 2007-07-26 13:04:40.000000000 -0300
  4742. @@ -0,0 +1,792 @@
  4743. +/* GCC rutime support routines for TI mode */
  4744. +
  4745. +/* Copyright (C) 2001 Sony Computer Entertainment Inc.
  4746. + Copyright 2001 Sony Corportaion. */
  4747. +
  4748. +/* This file is derived from libgcc2.c and subject to the original
  4749. + license of libgcc2.c, as follows. */
  4750. +
  4751. +/* Compile this one with gcc. */
  4752. +/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc.
  4753. +
  4754. +This file is part of GNU CC.
  4755. +
  4756. +GNU CC is free software; you can redistribute it and/or modify
  4757. +it under the terms of the GNU General Public License as published by
  4758. +the Free Software Foundation; either version 2, or (at your option)
  4759. +any later version.
  4760. +
  4761. +GNU CC is distributed in the hope that it will be useful,
  4762. +but WITHOUT ANY WARRANTY; without even the implied warranty of
  4763. +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  4764. +GNU General Public License for more details.
  4765. +
  4766. +You should have received a copy of the GNU General Public License
  4767. +along with GNU CC; see the file COPYING. If not, write to
  4768. +the Free Software Foundation, 59 Temple Place - Suite 330,
  4769. +Boston, MA 02111-1307, USA. */
  4770. +
  4771. +/* As a special exception, if you link this library with other files,
  4772. + some of which are compiled with GCC, to produce an executable,
  4773. + this library does not by itself cause the resulting executable
  4774. + to be covered by the GNU General Public License.
  4775. + This exception does not however invalidate any other reasons why
  4776. + the executable file might be covered by the GNU General Public License. */
  4777. +
  4778. +
  4779. +#include "tconfig.h"
  4780. +
  4781. +/* We disable this when inhibit_libc, so that gcc can still be built without
  4782. + needing header files first. */
  4783. +/* ??? This is not a good solution, since prototypes may be required in
  4784. + some cases for correct code. See also frame.c. */
  4785. +
  4786. +#include "machmode.h"
  4787. +#include "defaults.h"
  4788. +
  4789. +#ifndef LIBGCC2_WORDS_BIG_ENDIAN
  4790. +#define LIBGCC2_WORDS_BIG_ENDIAN WORDS_BIG_ENDIAN
  4791. +#endif
  4792. +
  4793. +
  4794. +/* In this file, we are interfacing to calls generated by the compiler
  4795. + itself. These calls pass values into these routines which have very
  4796. + specific modes (rather than very specific types), and these
  4797. + compiler-generated calls also expect any return values to have very
  4798. + specific modes (rather than very specific types). Thus, we need to
  4799. + avoid using regular C language type names in this part of the file
  4800. + because the sizes for those types can be configured to be anything.
  4801. + Instead we use the following special type names. */
  4802. +
  4803. +typedef unsigned int UTItype __attribute__((mode(TI)));
  4804. +typedef int TItype __attribute__((mode(TI)));
  4805. +typedef unsigned int UDItype __attribute__((mode(DI)));
  4806. +typedef int DItype __attribute__((mode(DI)));
  4807. +typedef unsigned int UQItype __attribute__((mode(QI)));
  4808. +typedef int QItype __attribute__((mode(QI)));
  4809. +
  4810. +typedef float SFtype __attribute__ ((mode (SF)));
  4811. +typedef float DFtype __attribute__ ((mode (DF)));
  4812. +
  4813. +typedef int word_type __attribute__ ((mode (__word__)));
  4814. +
  4815. +/* Make sure that we don't accidentally use any normal C language
  4816. + built-in type names in the first part of this file. Instead we want
  4817. + to use *only* the type names defined above.
  4818. + The following macro definitions insure that if we *do* accidentally
  4819. + use some normal C language built-in type name, we will get a syntax
  4820. + error. */
  4821. +
  4822. +#define char bogus_type
  4823. +#define short bogus_type
  4824. +#define int bogus_type
  4825. +#define long bogus_type
  4826. +#define unsigned bogus_type
  4827. +#define float bogus_type
  4828. +#define double bogus_type
  4829. +
  4830. +
  4831. +#ifndef BITS_PER_UNIT
  4832. +#define BITS_PER_UNIT 8
  4833. +#endif
  4834. +#ifndef DI_TYPE_SIZE
  4835. +#define DI_TYPE_SIZE 64
  4836. +#endif
  4837. +
  4838. +
  4839. +/* TIstructs are pairs of DItype values in the order determined by
  4840. + LIBGCC2_WORDS_BIG_ENDIAN. */
  4841. +
  4842. +#if LIBGCC2_WORDS_BIG_ENDIAN
  4843. +struct TIstruct {DItype high, low;};
  4844. +#else
  4845. +struct TIstruct {DItype low, high;};
  4846. +#endif
  4847. +
  4848. +/* We need this union to unpack/pack TImode values, since we don't have
  4849. + any arithmetic yet. Incoming TImode parameters are stored into the
  4850. + `ti' field, and the unpacked result is read from the struct `d'. */
  4851. +
  4852. +typedef union
  4853. +{
  4854. + struct TIstruct d;
  4855. + TItype ti;
  4856. +} TIunion;
  4857. +
  4858. +/* for
  4859. + __fixunsdfti
  4860. + __floattidf
  4861. + */
  4862. +#define DI_WORD_SIZE (sizeof (DItype) * BITS_PER_UNIT)
  4863. +#define HIGH_DI_WORD_COEFF (((UTItype) 1) << DI_WORD_SIZE)
  4864. +#define HIGH_DI_HALFWORD_COEFF (((UDItype) 1) << (DI_WORD_SIZE / 2))
  4865. +
  4866. +
  4867. +
  4868. +#if (defined (L_udivti3) || defined (L_divti3) || defined (L_multi3) ||\
  4869. + defined (L_umodti3) || defined (L_modti3))
  4870. +/* ----------------------------------------------------------------- */
  4871. +/* BEGIN: derived from longlog.h */
  4872. +/* for
  4873. + __udivmoddi4
  4874. + __multi3
  4875. + __dviti3
  4876. + __udviti3
  4877. + __modti3
  4878. + __umodti3
  4879. +*/
  4880. +
  4881. +#define __ti_B (((UDItype)1) << (DI_TYPE_SIZE / 2))
  4882. +#define __ti_lowpart(t) ((UDItype) (t) % __ti_B)
  4883. +#define __ti_highpart(t) ((UDItype) (t) / __ti_B)
  4884. +
  4885. +#define umul_ppmm_di(w1, w0, u, v) \
  4886. +do { \
  4887. + UDItype __x0, __x1, __x2, __x3; \
  4888. + UDItype __ul, __vl, __uh, __vh; \
  4889. + \
  4890. + __ul = __ti_lowpart (u); \
  4891. + __uh = __ti_highpart (u); \
  4892. + __vl = __ti_lowpart (v); \
  4893. + __vh = __ti_highpart (v); \
  4894. + \
  4895. + __x0 = (UDItype) __ul * __vl; \
  4896. + __x1 = (UDItype) __ul * __vh; \
  4897. + __x2 = (UDItype) __uh * __vl; \
  4898. + __x3 = (UDItype) __uh * __vh; \
  4899. + \
  4900. + __x1 += __ti_highpart (__x0);/* this can't give carry */ \
  4901. + __x1 += __x2; /* but this indeed can */ \
  4902. + if (__x1 < __x2) /* did we get it? */ \
  4903. + __x3 += __ti_B; /* yes, add it in the proper pos. */ \
  4904. + \
  4905. + (w1) = __x3 + __ti_highpart (__x1); \
  4906. + (w0) = __ti_lowpart (__x1) * __ti_B + __ti_lowpart (__x0); \
  4907. +} while (0)
  4908. +
  4909. +#define __umulditi3(u, v) \
  4910. + ({TIunion __w; \
  4911. + umul_ppmm_di (__w.d.high, __w.d.low, u, v); \
  4912. + __w.ti; })
  4913. +
  4914. +
  4915. +
  4916. +/* Define this unconditionally, so it can be used for debugging. */
  4917. +#define udiv_qrnnd_c_di(q, r, n1, n0, d) \
  4918. + do { \
  4919. + UDItype __d1, __d0, __q1, __q0; \
  4920. + UDItype __r1, __r0, __m; \
  4921. + __d1 = __ti_highpart (d); \
  4922. + __d0 = __ti_lowpart (d); \
  4923. + \
  4924. + __r1 = (n1) % __d1; \
  4925. + __q1 = (n1) / __d1; \
  4926. + __m = (UDItype) __q1 * __d0; \
  4927. + __r1 = __r1 * __ti_B | __ti_highpart (n0); \
  4928. + if (__r1 < __m) \
  4929. + { \
  4930. + __q1--, __r1 += (d); \
  4931. + if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
  4932. + if (__r1 < __m) \
  4933. + __q1--, __r1 += (d); \
  4934. + } \
  4935. + __r1 -= __m; \
  4936. + \
  4937. + __r0 = __r1 % __d1; \
  4938. + __q0 = __r1 / __d1; \
  4939. + __m = (UDItype) __q0 * __d0; \
  4940. + __r0 = __r0 * __ti_B | __ti_lowpart (n0); \
  4941. + if (__r0 < __m) \
  4942. + { \
  4943. + __q0--, __r0 += (d); \
  4944. + if (__r0 >= (d)) \
  4945. + if (__r0 < __m) \
  4946. + __q0--, __r0 += (d); \
  4947. + } \
  4948. + __r0 -= __m; \
  4949. + \
  4950. + (q) = (UDItype) __q1 * __ti_B | __q0; \
  4951. + (r) = __r0; \
  4952. + } while (0)
  4953. +
  4954. +
  4955. +#define sub_ddmmss_di(sh, sl, ah, al, bh, bl) \
  4956. + do { \
  4957. + UDItype __x; \
  4958. + __x = (al) - (bl); \
  4959. + (sh) = (ah) - (bh) - (__x > (al)); \
  4960. + (sl) = __x; \
  4961. + } while (0)
  4962. +
  4963. +#define count_leading_zeros_di(count, x) \
  4964. + do { \
  4965. + UDItype __xr = (x); \
  4966. + UDItype __a; \
  4967. + \
  4968. + { \
  4969. + for (__a = DI_TYPE_SIZE - 8; __a > 0; __a -= 8) \
  4970. + if (((__xr >> __a) & 0xff) != 0) \
  4971. + break; \
  4972. + } \
  4973. + \
  4974. + (count) = DI_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
  4975. + } while (0)
  4976. +
  4977. +
  4978. +
  4979. +/* END: derived from longlog.h */
  4980. +/* ----------------------------------------------------------------- */
  4981. +#endif /* (defined (L_udivti3) || defined (L_divti3) || defined (L_multi3) ||
  4982. + defined (L_umodti3) || defined (L_modti3)) */
  4983. +
  4984. +
  4985. +#if defined (L_negti2) || defined (L_divti3) || defined (L_modti3)
  4986. +#if defined (L_divti3) || defined (L_modti3)
  4987. +static inline
  4988. +#endif
  4989. +TItype
  4990. +__negti2 (TItype u)
  4991. +{
  4992. + TIunion w;
  4993. + TIunion uu;
  4994. +
  4995. + uu.ti = u;
  4996. +
  4997. + w.d.low = -uu.d.low;
  4998. + w.d.high = -uu.d.high - ((UDItype) w.d.low > 0);
  4999. +
  5000. + return w.ti;
  5001. +}
  5002. +#endif
  5003. +
  5004. +/* Unless shift functions are defined whith full ANSI prototypes,
  5005. + parameter b will be promoted to int if word_type is smaller than an int. */
  5006. +#ifdef L_lshrti3
  5007. +TItype
  5008. +__lshrti3 (TItype u, word_type b)
  5009. +{
  5010. + TIunion w;
  5011. + word_type bm;
  5012. + TIunion uu;
  5013. +
  5014. + if (b == 0)
  5015. + return u;
  5016. +
  5017. + uu.ti = u;
  5018. +
  5019. + bm = (sizeof (DItype) * BITS_PER_UNIT) - b;
  5020. + if (bm <= 0)
  5021. + {
  5022. + w.d.high = 0;
  5023. + w.d.low = (UDItype)uu.d.high >> -bm;
  5024. + }
  5025. + else
  5026. + {
  5027. + UDItype carries = (UDItype)uu.d.high << bm;
  5028. + w.d.high = (UDItype)uu.d.high >> b;
  5029. + w.d.low = ((UDItype)uu.d.low >> b) | carries;
  5030. + }
  5031. +
  5032. + return w.ti;
  5033. +}
  5034. +#endif
  5035. +
  5036. +#ifdef L_ashlti3
  5037. +TItype
  5038. +__ashlti3 (TItype u, word_type b)
  5039. +{
  5040. + TIunion w;
  5041. + word_type bm;
  5042. + TIunion uu;
  5043. +
  5044. + if (b == 0)
  5045. + return u;
  5046. +
  5047. + uu.ti = u;
  5048. +
  5049. + bm = (sizeof (DItype) * BITS_PER_UNIT) - b;
  5050. + if (bm <= 0)
  5051. + {
  5052. + w.d.low = 0;
  5053. + w.d.high = (UDItype)uu.d.low << -bm;
  5054. + }
  5055. + else
  5056. + {
  5057. + UDItype carries = (UDItype)uu.d.low >> bm;
  5058. + w.d.low = (UDItype)uu.d.low << b;
  5059. + w.d.high = ((UDItype)uu.d.high << b) | carries;
  5060. + }
  5061. +
  5062. + return w.ti;
  5063. +}
  5064. +#endif
  5065. +
  5066. +#ifdef L_ashrti3
  5067. +TItype
  5068. +__ashrti3 (TItype u, word_type b)
  5069. +{
  5070. + TIunion w;
  5071. + word_type bm;
  5072. + TIunion uu;
  5073. +
  5074. + if (b == 0)
  5075. + return u;
  5076. +
  5077. + uu.ti = u;
  5078. +
  5079. + bm = (sizeof (DItype) * BITS_PER_UNIT) - b;
  5080. + if (bm <= 0)
  5081. + {
  5082. + /* w.d.high = 1..1 or 0..0 */
  5083. + w.d.high = uu.d.high >> (sizeof (DItype) * BITS_PER_UNIT - 1);
  5084. + w.d.low = uu.d.high >> -bm;
  5085. + }
  5086. + else
  5087. + {
  5088. + UDItype carries = (UDItype)uu.d.high << bm;
  5089. + w.d.high = uu.d.high >> b;
  5090. + w.d.low = ((UDItype)uu.d.low >> b) | carries;
  5091. + }
  5092. +
  5093. + return w.ti;
  5094. +}
  5095. +#endif
  5096. +
  5097. +#ifdef L_ffsti2
  5098. +TItype
  5099. +__ffsti2 (TItype u)
  5100. +{
  5101. + TIunion uu, w;
  5102. + uu.ti = u;
  5103. + w.d.high = 0;
  5104. + w.d.low = __ffsdi2 (uu.d.low);
  5105. + if (w.d.low != 0)
  5106. + return w.ti;
  5107. + w.d.low = __ffsdi2 (uu.d.high);
  5108. + if (w.d.low != 0)
  5109. + {
  5110. + w.d.low += BITS_PER_UNIT * sizeof (DItype);
  5111. + return w.ti;
  5112. + }
  5113. + return w.ti;
  5114. +}
  5115. +#endif
  5116. +
  5117. +
  5118. +#ifdef L_multi3
  5119. +TItype
  5120. +__multi3 (TItype u, TItype v)
  5121. +{
  5122. + TIunion w;
  5123. + TIunion uu, vv;
  5124. +
  5125. + uu.ti = u,
  5126. + vv.ti= v;
  5127. +
  5128. + w.ti = __umulditi3 (uu.d.low, vv.d.low);
  5129. + w.d.high += ((UDItype) uu.d.low * (UDItype) vv.d.high
  5130. + + (UDItype) uu.d.high * (UDItype) vv.d.low);
  5131. +
  5132. + return w.ti;
  5133. +}
  5134. +#endif
  5135. +
  5136. +#if (defined (L_udivti3) || defined (L_divti3) || \
  5137. + defined (L_umodti3) || defined (L_modti3))
  5138. +#define L_udivmodti4
  5139. +#endif
  5140. +
  5141. +#ifdef L_udivmodti4
  5142. +static const UQItype __clz_tab[] =
  5143. +{
  5144. + 0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
  5145. + 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
  5146. + 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
  5147. + 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
  5148. + 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
  5149. + 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
  5150. + 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
  5151. + 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
  5152. +};
  5153. +
  5154. +#if (defined (L_udivti3) || defined (L_divti3) || \
  5155. + defined (L_umodti3) || defined (L_modti3))
  5156. +static inline
  5157. +#endif
  5158. +UTItype
  5159. +__udivmodti4 (UTItype n, UTItype d, UTItype *rp)
  5160. +{
  5161. + TIunion ww;
  5162. + TIunion nn, dd;
  5163. + TIunion rr;
  5164. + UDItype d0, d1, n0, n1, n2;
  5165. + UDItype q0, q1;
  5166. + UDItype b, bm;
  5167. +
  5168. + nn.ti = n;
  5169. + dd.ti = d;
  5170. +
  5171. + d0 = dd.d.low;
  5172. + d1 = dd.d.high;
  5173. + n0 = nn.d.low;
  5174. + n1 = nn.d.high;
  5175. +
  5176. +
  5177. + if (d1 == 0)
  5178. + {
  5179. + if (d0 > n1)
  5180. + {
  5181. + /* 0q = nn / 0D */
  5182. +
  5183. + count_leading_zeros_di (bm, d0);
  5184. +
  5185. + if (bm != 0)
  5186. + {
  5187. + /* Normalize, i.e. make the most significant bit of the
  5188. + denominator set. */
  5189. +
  5190. + d0 = d0 << bm;
  5191. + n1 = (n1 << bm) | (n0 >> (DI_TYPE_SIZE - bm));
  5192. + n0 = n0 << bm;
  5193. + }
  5194. +
  5195. + udiv_qrnnd_c_di (q0, n0, n1, n0, d0);
  5196. + q1 = 0;
  5197. +
  5198. + /* Remainder in n0 >> bm. */
  5199. + }
  5200. + else
  5201. + {
  5202. + /* qq = NN / 0d */
  5203. +
  5204. + if (d0 == 0)
  5205. + d0 = 1 / d0; /* Divide intentionally by zero. */
  5206. +
  5207. + count_leading_zeros_di (bm, d0);
  5208. +
  5209. + if (bm == 0)
  5210. + {
  5211. + /* From (n1 >= d0) /\ (the most significant bit of d0 is set),
  5212. + conclude (the most significant bit of n1 is set) /\ (the
  5213. + leading quotient digit q1 = 1).
  5214. +
  5215. + This special case is necessary, not an optimization.
  5216. + (Shifts counts of DI_TYPE_SIZE are undefined.) */
  5217. +
  5218. + n1 -= d0;
  5219. + q1 = 1;
  5220. + }
  5221. + else
  5222. + {
  5223. + /* Normalize. */
  5224. +
  5225. + b = DI_TYPE_SIZE - bm;
  5226. +
  5227. + d0 = d0 << bm;
  5228. + n2 = n1 >> b;
  5229. + n1 = (n1 << bm) | (n0 >> b);
  5230. + n0 = n0 << bm;
  5231. +
  5232. + udiv_qrnnd_c_di (q1, n1, n2, n1, d0);
  5233. + }
  5234. +
  5235. + /* n1 != d0... */
  5236. +
  5237. + udiv_qrnnd_c_di (q0, n0, n1, n0, d0);
  5238. +
  5239. + /* Remainder in n0 >> bm. */
  5240. + }
  5241. +
  5242. + if (rp != 0)
  5243. + {
  5244. + rr.d.low = n0 >> bm;
  5245. + rr.d.high = 0;
  5246. + *rp = rr.ti;
  5247. + }
  5248. + }
  5249. + else
  5250. + {
  5251. + if (d1 > n1)
  5252. + {
  5253. + /* 00 = nn / DD */
  5254. +
  5255. + q0 = 0;
  5256. + q1 = 0;
  5257. +
  5258. + /* Remainder in n1n0. */
  5259. + if (rp != 0)
  5260. + {
  5261. + rr.d.low = n0;
  5262. + rr.d.high = n1;
  5263. + *rp = rr.ti;
  5264. + }
  5265. + }
  5266. + else
  5267. + {
  5268. + /* 0q = NN / dd */
  5269. +
  5270. + count_leading_zeros_di (bm, d1);
  5271. + if (bm == 0)
  5272. + {
  5273. + /* From (n1 >= d1) /\ (the most significant bit of d1 is set),
  5274. + conclude (the most significant bit of n1 is set) /\ (the
  5275. + quotient digit q0 = 0 or 1).
  5276. +
  5277. + This special case is necessary, not an optimization. */
  5278. +
  5279. + /* The condition on the next line takes advantage of that
  5280. + n1 >= d1 (true due to program flow). */
  5281. + if (n1 > d1 || n0 >= d0)
  5282. + {
  5283. + q0 = 1;
  5284. + sub_ddmmss_di (n1, n0, n1, n0, d1, d0);
  5285. + }
  5286. + else
  5287. + q0 = 0;
  5288. +
  5289. + q1 = 0;
  5290. +
  5291. + if (rp != 0)
  5292. + {
  5293. + rr.d.low = n0;
  5294. + rr.d.high = n1;
  5295. + *rp = rr.ti;
  5296. + }
  5297. + }
  5298. + else
  5299. + {
  5300. + UDItype m1, m0;
  5301. + /* Normalize. */
  5302. +
  5303. + b = DI_TYPE_SIZE - bm;
  5304. +
  5305. + d1 = (d1 << bm) | (d0 >> b);
  5306. + d0 = d0 << bm;
  5307. + n2 = n1 >> b;
  5308. + n1 = (n1 << bm) | (n0 >> b);
  5309. + n0 = n0 << bm;
  5310. +
  5311. + udiv_qrnnd_c_di (q0, n1, n2, n1, d1);
  5312. + umul_ppmm_di (m1, m0, q0, d0);
  5313. +
  5314. + if (m1 > n1 || (m1 == n1 && m0 > n0))
  5315. + {
  5316. + q0--;
  5317. + sub_ddmmss_di (m1, m0, m1, m0, d1, d0);
  5318. + }
  5319. +
  5320. + q1 = 0;
  5321. +
  5322. + /* Remainder in (n1n0 - m1m0) >> bm. */
  5323. + if (rp != 0)
  5324. + {
  5325. + sub_ddmmss_di (n1, n0, n1, n0, m1, m0);
  5326. + rr.d.low = (n1 << b) | (n0 >> bm);
  5327. + rr.d.high = n1 >> bm;
  5328. + *rp = rr.ti;
  5329. + }
  5330. + }
  5331. + }
  5332. + }
  5333. +
  5334. + ww.d.low = q0;
  5335. + ww.d.high = q1;
  5336. + return ww.ti;
  5337. +}
  5338. +#endif
  5339. +
  5340. +#ifdef L_divti3
  5341. +UTItype __udivmodti4 ();
  5342. +
  5343. +TItype
  5344. +__divti3 (TItype u, TItype v)
  5345. +{
  5346. + word_type c = 0;
  5347. + TIunion uu, vv;
  5348. + TItype w;
  5349. +
  5350. + uu.ti = u;
  5351. + vv.ti = v;
  5352. +
  5353. + if (uu.d.high < 0)
  5354. + c = ~c,
  5355. + uu.ti = __negti2 (uu.ti);
  5356. + if (vv.d.high < 0)
  5357. + c = ~c,
  5358. + vv.ti = __negti2 (vv.ti);
  5359. +
  5360. + w = __udivmodti4 (uu.ti, vv.ti, (UTItype *) 0);
  5361. + if (c)
  5362. + w = __negti2 (w);
  5363. +
  5364. + return w;
  5365. +}
  5366. +#endif
  5367. +
  5368. +#ifdef L_modti3
  5369. +UTItype __udivmodti4 ();
  5370. +
  5371. +TItype
  5372. +__modti3 (TItype u, TItype v)
  5373. +{
  5374. + word_type c = 0;
  5375. + TIunion uu, vv;
  5376. + TItype w;
  5377. +
  5378. + uu.ti = u;
  5379. + vv.ti = v;
  5380. +
  5381. + if (uu.d.high < 0)
  5382. + c = ~c,
  5383. + uu.ti = __negti2 (uu.ti);
  5384. + if (vv.d.high < 0)
  5385. + vv.ti = __negti2 (vv.ti);
  5386. +
  5387. + (void) __udivmodti4 (uu.ti, vv.ti, (UTItype *)&w);
  5388. + if (c)
  5389. + w = __negti2 (w);
  5390. +
  5391. + return w;
  5392. +}
  5393. +#endif
  5394. +
  5395. +#ifdef L_umodti3
  5396. +UTItype __udivmodti4 ();
  5397. +
  5398. +UTItype
  5399. +__umodti3 (UTItype u, UTItype v)
  5400. +{
  5401. + UTItype w;
  5402. +
  5403. + (void) __udivmodti4 (u, v, &w);
  5404. +
  5405. + return w;
  5406. +}
  5407. +#endif
  5408. +
  5409. +
  5410. +#ifdef L_udivti3
  5411. +UTItype __udivmodti4 ();
  5412. +UTItype
  5413. +__udivti3 (UTItype n, UTItype d)
  5414. +{
  5415. + return __udivmodti4 (n, d, (UTItype *) 0);
  5416. +}
  5417. +#endif
  5418. +
  5419. +#ifdef L_cmpti2
  5420. +word_type
  5421. +__cmpti2 (TItype a, TItype b)
  5422. +{
  5423. + TIunion au, bu;
  5424. +
  5425. + au.ti = a, bu.ti = b;
  5426. +
  5427. + if (au.d.high < bu.d.high)
  5428. + return 0;
  5429. + else if (au.d.high > bu.d.high)
  5430. + return 2;
  5431. + if ((UDItype) au.d.low < (UDItype) bu.d.low)
  5432. + return 0;
  5433. + else if ((UDItype) au.d.low > (UDItype) bu.d.low)
  5434. + return 2;
  5435. + return 1;
  5436. +}
  5437. +#endif
  5438. +
  5439. +#ifdef L_ucmpti2
  5440. +word_type
  5441. +__ucmpti2 (UTItype a, UTItype b)
  5442. +{
  5443. + TIunion au, bu;
  5444. +
  5445. + au.ti = a, bu.ti = b;
  5446. +
  5447. + if ((UDItype) au.d.high < (UDItype) bu.d.high)
  5448. + return 0;
  5449. + else if ((UDItype) au.d.high > (UDItype) bu.d.high)
  5450. + return 2;
  5451. + if ((UDItype) au.d.low < (UDItype) bu.d.low)
  5452. + return 0;
  5453. + else if ((UDItype) au.d.low > (UDItype) bu.d.low)
  5454. + return 2;
  5455. + return 1;
  5456. +}
  5457. +#endif
  5458. +
  5459. +
  5460. +/*
  5461. + Followings are not neeeded, because TF or XF mode is not supported.
  5462. + __fixunstfti(), __fixtfdi()
  5463. + __fixunsxfti(), __fixxfti()
  5464. +*/
  5465. +
  5466. +#ifdef L_fixunsdfti
  5467. +TItype
  5468. +__fixunsdfti (DFtype a)
  5469. +{
  5470. + DFtype b;
  5471. + UTItype v;
  5472. +
  5473. + if (a < 0)
  5474. + return 0;
  5475. +
  5476. + /* Compute high word of result, as a flonum. */
  5477. + b = (a / HIGH_DI_WORD_COEFF);
  5478. + /* Convert that to fixed (but not to DItype!),
  5479. + and shift it into the high word. */
  5480. + v = (UDItype) b;
  5481. + v <<= DI_WORD_SIZE;
  5482. + /* Remove high part from the DFtype, leaving the low part as flonum. */
  5483. + a -= (DFtype)v;
  5484. + /* Convert that to fixed (but not to DItype!) and add it in.
  5485. + Sometimes A comes out negative. This is significant, since
  5486. + A has more bits than a long int does. */
  5487. + if (a < 0)
  5488. + v -= (UDItype) (- a);
  5489. + else
  5490. + v += (UDItype) a;
  5491. + return v;
  5492. +}
  5493. +#endif
  5494. +
  5495. +#ifdef L_fixdfti
  5496. +TItype
  5497. +__fixdfti (DFtype a)
  5498. +{
  5499. + if (a < 0)
  5500. + return - __fixunsdfti (-a);
  5501. + return __fixunsdfti (a);
  5502. +}
  5503. +#endif
  5504. +
  5505. +/*
  5506. + Followings are not neeeded, because TF or XF mode is not supported.
  5507. + __floattixf
  5508. + __floattitf
  5509. +*/
  5510. +
  5511. +#ifdef L_floattidf
  5512. +DFtype
  5513. +__floattidf (TItype u)
  5514. +{
  5515. + DFtype d;
  5516. +
  5517. + d = (DItype) (u >> DI_WORD_SIZE);
  5518. + d *= HIGH_DI_HALFWORD_COEFF;
  5519. + d *= HIGH_DI_HALFWORD_COEFF;
  5520. + d += (UDItype) (u & (HIGH_DI_WORD_COEFF - 1));
  5521. +
  5522. + return d;
  5523. +}
  5524. +#endif
  5525. +
  5526. +#ifdef L_floattisf
  5527. +SFtype
  5528. +__floattisf (TItype u)
  5529. +{
  5530. + DFtype df;
  5531. + df = __floattidf (u);
  5532. + return (SFtype) df;
  5533. +}
  5534. +#endif
  5535. diff -burN orig.gcc-3.2.3/gcc/Makefile.in gcc-3.2.3/gcc/Makefile.in
  5536. --- orig.gcc-3.2.3/gcc/Makefile.in 2003-01-28 17:54:07.000000000 -0400
  5537. +++ gcc-3.2.3/gcc/Makefile.in 2007-07-26 13:04:40.000000000 -0300
  5538. @@ -987,6 +987,7 @@
  5539. LIB2FUNCS_ST='$(LIB2FUNCS_ST)' \
  5540. LIB2ADD='$(LIB2ADD)' \
  5541. LIB2ADD_ST='$(LIB2ADD_ST)' \
  5542. + LIB2FUNCS_TI='$(LIB2FUNCS_TI)' \
  5543. LIB2ADDEH='$(LIB2ADDEH)' \
  5544. LIB2ADDEHDEP='$(LIB2ADDEHDEP)' \
  5545. FPBIT='$(FPBIT)' \
  5546. diff -burN orig.gcc-3.2.3/gcc/collect2.c gcc-3.2.3/gcc/collect2.c
  5547. --- orig.gcc-3.2.3/gcc/collect2.c 2009-08-19 16:36:00.000000000 -0500
  5548. +++ gcc-3.2.3/gcc/collect2.c 2009-08-19 16:36:11.000000000 -0500
  5549. @@ -1587,7 +1587,7 @@
  5550. if (redir)
  5551. {
  5552. /* Open response file. */
  5553. - redir_handle = open (redir, O_WRONLY | O_TRUNC | O_CREAT);
  5554. + redir_handle = open (redir, O_WRONLY | O_TRUNC | O_CREAT, 0666);
  5555.  
  5556. /* Duplicate the stdout and stderr file handles
  5557. so they can be restored later. */
  5558. diff -burN orig.gcc-3.2.3/gcc/mklibgcc.in gcc-3.2.3/gcc/mklibgcc.in
  5559. --- orig.gcc-3.2.3/gcc/mklibgcc.in 2003-01-28 17:57:40.000000000 -0400
  5560. +++ gcc-3.2.3/gcc/mklibgcc.in 2007-07-26 13:04:40.000000000 -0300
  5561. @@ -232,6 +232,21 @@
  5562. libgcc2_st_objs="$libgcc2_st_objs ${oname}${objext}"
  5563. done
  5564.  
  5565. +if [ "$LIB2FUNCS_TI" ]; then
  5566. + for name in $LIB2FUNCS_TI; do
  5567. + for ml in $MULTILIBS; do
  5568. + dir=`echo ${ml} | sed -e 's/;.*$//' -e 's/=/$(EQ)/g'`
  5569. + flags=`echo ${ml} | sed -e 's/^[^;]*;//' -e 's/@/ -/g'`;
  5570. + out="libgcc/${dir}/${name}${objext}"
  5571. +
  5572. + echo $out: $libgcc2_c_dep
  5573. + echo " $gcc_compile" '$(MAYBE_USE_COLLECT2)' $flags -DL$name \
  5574. + -c '$(srcdir)/libgcc2-timode.c' -o $out
  5575. + done
  5576. + libgcc2_objs="$libgcc2_objs ${name}${objext}"
  5577. + done
  5578. +fi
  5579. +
  5580. # SHLIB_MKMAP
  5581. # SHLIB_MKMAP_OPTS
  5582. # SHLIB_MAPFILES
  5583. diff -burN orig.gcc-3.2.3/gcc/toplev.c gcc-3.2.3/gcc/toplev.c
  5584. --- orig.gcc-3.2.3/gcc/toplev.c 2002-11-01 20:57:23.000000000 -0400
  5585. +++ gcc-3.2.3/gcc/toplev.c 2007-07-26 13:04:40.000000000 -0300
  5586. @@ -3469,6 +3469,18 @@
  5587.  
  5588. convert_to_eh_region_ranges ();
  5589.  
  5590. +#ifdef MACHINE_DEPENDENT_REORG_FINAL
  5591. + timevar_push (TV_MACH_DEP);
  5592. + open_dump_file (DFI_mach, decl);
  5593. +
  5594. + MACHINE_DEPENDENT_REORG_FINAL (insns);
  5595. +
  5596. + close_dump_file (DFI_mach, print_rtl, insns);
  5597. + timevar_pop (TV_MACH_DEP);
  5598. +
  5599. + ggc_collect ();
  5600. +#endif
  5601. +
  5602. /* Shorten branches. */
  5603. timevar_push (TV_SHORTEN_BRANCH);
  5604. shorten_branches (get_insns ());
  5605. diff -burN orig.gcc-3.2.3/include/obstack.h gcc-3.2.3/include/obstack.h
  5606. --- orig.gcc-3.2.3/include/obstack.h 2001-03-14 15:44:38.000000000 -0400
  5607. +++ gcc-3.2.3/include/obstack.h 2007-07-26 13:04:40.000000000 -0300
  5608. @@ -423,7 +423,8 @@
  5609. ({ struct obstack *__o = (OBSTACK); \
  5610. if (__o->next_free + sizeof (void *) > __o->chunk_limit) \
  5611. _obstack_newchunk (__o, sizeof (void *)); \
  5612. - *((void **)__o->next_free)++ = ((void *)datum); \
  5613. + *((void **)__o->next_free) = ((void *)datum); \
  5614. + __o->next_free += sizeof(void *); \
  5615. (void) 0; })
  5616.  
  5617. # define obstack_int_grow(OBSTACK,datum) \
  5618. diff -burN orig.gcc-3.2.3/libstdc++-v3/configure.target gcc-3.2.3/libstdc++-v3/configure.target
  5619. --- orig.gcc-3.2.3/libstdc++-v3/configure.target 2002-09-06 15:32:08.000000000 -0300
  5620. +++ gcc-3.2.3/libstdc++-v3/configure.target 2007-07-26 13:04:40.000000000 -0300
  5621. @@ -55,6 +55,9 @@
  5622. m68k | m680[246]0)
  5623. cpu_include_dir="config/cpu/m68k"
  5624. ;;
  5625. + mips)
  5626. + cpu_include_dir="config/cpu/mips"
  5627. + ;;
  5628. powerpc | rs6000)
  5629. cpu_include_dir="config/cpu/powerpc"
  5630. ;;
  5631. diff -burN orig.gcc-3.2.3/libstdc++-v3/libsupc++/pure.cc gcc-3.2.3/libstdc++-v3/libsupc++/pure.cc
  5632. --- orig.gcc-3.2.3/libstdc++-v3/libsupc++/pure.cc 2002-06-28 05:22:38.000000000 -0300
  5633. +++ gcc-3.2.3/libstdc++-v3/libsupc++/pure.cc 2007-07-26 13:04:40.000000000 -0300
  5634. @@ -46,6 +46,6 @@
  5635. extern "C" void
  5636. __cxa_pure_virtual (void)
  5637. {
  5638. - writestr ("pure virtual method called\n");
  5639. +// writestr ("pure virtual method called\n");
  5640. std::terminate ();
  5641. }
  5642. diff -burN orig.gcc-3.2.3/README.PS2 gcc-3.2.3/README.PS2
  5643. --- orig.gcc-3.2.3/README.PS2 1969-12-31 20:00:00.000000000 -0400
  5644. +++ gcc-3.2.3/README.PS2 2007-07-26 13:04:40.000000000 -0300
  5645. @@ -0,0 +1,80 @@
  5646. +Apologies to mrbrown, who's README.PS2 this was based on.
  5647. +GCC for Sony Playstation 2
  5648. +http://www.ps2dev.org/
  5649. +BETA 3 Release 3.2.3-20040214-1
  5650. +==
  5651. +
  5652. +This patch contains a port of the GNU Compiler Collection (http://gcc.gnu.org)
  5653. +version 3.2.3 (prerelease) to the Sony Playstation 2. It supports a C and C++
  5654. +cross-compiler targeting the Emotion Engine (Toshiba MIPS R5900). It is based
  5655. +off of the port that Cygnus (now Red Hat) created for the original PS2 SDK,
  5656. +and contains a number of changes and updates that mrbrown has incorporated,
  5657. +plus some fixes by me.
  5658. +
  5659. +Unfortunately, there is no ChangeLog in this release.
  5660. +
  5661. +The Playstation 2 Linux kit is NOT supported in this release. There are a
  5662. +number of issues related to the deployment of this version of GCC in that
  5663. +environment. This is left as an exercise for the ps2linux folks.
  5664. +
  5665. +You can grab the source to the GCC 3.2.3 release from
  5666. +ftp://ftp.gnu.org/pub/gnu/gcc/gcc-3.2.3.tar.gz or a mirror site.
  5667. +
  5668. +
  5669. +Features
  5670. +--
  5671. +
  5672. +- Basic support for the R5900 and COP1.
  5673. +- Initial support for 128-bit logical/arith operations (pand, pnor, etc.).
  5674. +- Initial support for MMI built-in functions (__builtin_paddb, etc.) and vector
  5675. + types.
  5676. +- The main "feature" of this release is the port to the 3.2.3 compiler and fixes
  5677. + to the HILO1 code, allowing re-enabling of double precision emulation and also
  5678. + C++ global constructor fixes. This release may fix the 64bit shift bug, but
  5679. + if that's the case then it's a side effect of another fix.
  5680. +- Used in conjunction with my binutils-2.13.2.1 patch, you should be able to use
  5681. + -O0 and -O1 without causing bad code generation.
  5682. +- Alignment in bss sections bug fix.
  5683. +
  5684. +To configure the compiler, you can use one of the following configuration
  5685. +names:
  5686. +
  5687. + ee, mips64r5900[el], mipsEE[el]
  5688. +
  5689. +If you don't specify the OS portion of the name, -elf is assumed. Note that
  5690. +even if you leave off the "el", you cannot build for big-endian R5900 (it's
  5691. +explicitly disabled). I always use "ee".
  5692. +
  5693. +
  5694. +Known Bugs
  5695. +--
  5696. +
  5697. +[ I haven't found any serious codegen bugs yet. Mail to the ps2dev forums if
  5698. + you find any. ]
  5699. +
  5700. + If you wish to disable double precision emulation, comment out the text around
  5701. + DPBIT (and the make target that follows it) in gcc/config/mips/t-r5900. If you
  5702. + comment this section out and use double precision FP in your code, you WILL
  5703. + receive link errors when linking with libgcc. You can use this "feature" as a
  5704. + tool to find all misuses of float constants and type conversions in your code.
  5705. + Personally, I had trouble getting libstdc++-v3 to build without double precision
  5706. + emulation but YMMV. It should be possible to configure the compiler and libs
  5707. + to use single precision doubles in place of doubles, however you'd have to make
  5708. + sure that all your libs are built in this manner.
  5709. +
  5710. +
  5711. +Future Work
  5712. +--
  5713. +
  5714. + Move over to gcc 3.4, once it's released. gcc 3.4 includes a re-write of the
  5715. + entire mips back end and it looks a lot cleaner.
  5716. +
  5717. +
  5718. +Contact
  5719. +--
  5720. +
  5721. + Use the forums at www.ps2dev.org or find me on IRC at #ps2dev on EFnet.
  5722. +
  5723. +--
  5724. +MrHTFord (mrhtford_ps2dev@hotmail.com)
  5725. +Friday 14th February 2004.
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