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  1. module disp_7seg(b, HEX);
  2.     input [3:0] b;
  3.     output [7:0] HEX;
  4.    
  5.     assign HEX[0] = (~b[3]&~b[2]&~b[1]&b[0]) | (~b[3]&b[2]&~b[1]&~b[0]);
  6.     assign HEX[1] = (~b[3]&b[2]&~b[1]&b[0]) | (~b[3]&b[2]&b[1]&~b[0]);
  7.     assign HEX[2] = (~b[3]&~b[2]&b[1]&~b[0]);
  8.     assign HEX[3] = (~b[3]&~b[2]&~b[1]&b[0]) | (~b[3]&b[2]&~b[1]&~b[0]) | (~b[3]&b[2]&b[1]&b[0]);
  9.     assign HEX[4] = ~( (~b[3]&~b[2]&~b[1]&~b[0]) | (~b[3]&~b[2]&b[1]&~b[0]) | (~b[3]&b[2]&b[1]&~b[0]) | (b[3]&~b[2]&~b[1]&~b[0])  );
  10.     assign HEX[5] = (~b[3]&~b[2]&~b[1]&b[0]) | (~b[3]&~b[2]&b[1]&~b[0]) | (~b[3]&~b[2]&b[1]&b[0]);
  11.     assign HEX[6] = (~b[3]&~b[2]&~b[1]&~b[0]) | (~b[3]&~b[2]&~b[1]&b[0]) | (~b[3]&b[2]&b[1]&b[0]);
  12. endmodule
  13.  
  14. // minutos
  15. module firstCounter(Clk, vaiUm, digDir, digEsq);
  16.     input Clk;
  17.     output reg vaiUm;
  18.     output reg [3:0] digDir, digEsq;
  19.    
  20.     initial begin
  21.         digDir = 4'b0;
  22.         digEsq = 4'b0;
  23.     end
  24.    
  25.     always @( posedge Clk ) begin
  26.         if(~digEsq[3] & digEsq[2] & ~digEsq[1] & digEsq[0] & digDir[3] & ~digDir[2] & ~digDir[1] & digDir[0] ) begin
  27.             vaiUm = 1;
  28.             digDir = 4'b0;
  29.             digEsq = 4'b0;
  30.         end else begin
  31.             vaiUm = 0;
  32.             if(digDir[0] & ~digDir[1] & ~digDir[2] & digDir[3]) begin // reseta em 9
  33.                 digDir = 4'b0;
  34.                 digEsq = digEsq + 1;
  35.             end else begin
  36.                 digDir = digDir + 1;
  37.             end
  38.         end
  39.     end
  40. endmodule
  41.  
  42. // horas
  43. module secondCounter(Clk, vaiUm, digDir, digEsq);
  44.     input Clk;
  45.     output reg vaiUm;
  46.     output reg [3:0] digDir, digEsq;
  47.    
  48.     initial begin
  49.         digDir = 4'b0;
  50.         digEsq = 4'b0;
  51.     end
  52.    
  53.     always @( posedge Clk ) begin
  54.         if(~digEsq[3] & ~digEsq[2] & digEsq[1] & ~digEsq[0] & ~digDir[3] & ~digDir[2] & digDir[1] & digDir[0]) begin
  55.             vaiUm = 1;
  56.             digDir = 4'b0;
  57.             digEsq = 4'b0;
  58.         end else begin
  59.             vaiUm = 0;
  60.             if(digDir[0] & ~digDir[1] & ~digDir[2] & digDir[3]) begin
  61.                 digDir[3:0] = 4'b0;
  62.                 digEsq <= digEsq + 1;
  63.             end else begin
  64.                 digDir <= digDir + 1;
  65.             end
  66.         end
  67.     end
  68. endmodule
  69.  
  70.  
  71. module teste(Clk, HourLef, HourRig, MinLef, MinRig );
  72.     input Clk;
  73.     output [3:0] MinLef, MinRig, HourLef, HourRig;
  74.    
  75.     wire [1:0] vaiUm;
  76.     firstCounter fc(Clk , vaiUm[0], MinRig, MinLef);
  77.     secondCounter sc(vaiUm[0], vaiUm[1], HourRig, HourLef);
  78. endmodule
  79.  
  80. module top(SW, KEY, HEX0, HEX1, HEX2, HEX3);
  81.     input [17:0] SW;
  82.     input [3:0] KEY;
  83.     output [7:0] HEX0, HEX1, HEX2, HEX3;
  84.    
  85.     wire [7:0] left, right;
  86.     teste(KEY[3], left[7:4], left[3:0], right[7:4], right[3:0]);
  87.    
  88.     disp_7seg d1(right[3:0], HEX0);
  89.     disp_7seg d2(right[7:4], HEX1);
  90.     disp_7seg d3(left[3:0], HEX2);
  91.     disp_7seg d4(left[7:4], HEX3);
  92. endmodule
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