entity sumator is
	port (A,B,Ci : in bit;
		  Co,S : out bit);
end sumator;

architecture sum of sumator is
begin
	S <= A xor B xor Ci;

	process(A,B,Ci)
	begin
		if ((A xor B) = '0') then Co <= B;
		else Co <= Ci;
		end if;
	end process;
end sum;


entity sumator4bit is
	port (A,B : in bit_vector(3 downto 0);
		Ci : in bit;
		S : out bit_vector(3 downto 0);
		Co : out bit);
end sumator4bit;

architecture sum4bit of sumator4bit is

component sumator
	port (A,B,Ci : in bit;
		  Co,S : out bit);
end component;

signal Internal: bit_vector(2 downto 0);

begin
	S1: sumator port map (A[0], B[0], Ci, Internal[0], S[0]);
	S2: sumator port map (A[1], B[1], Internal[0], Internal[1], S[1]);
	S3: sumator port map (A[2], B[2], Internal[1], Internal[2], S[2]);
	S4: sumator port map (A[3], B[3], Internal[2], Co, S[3]);
end sum4bit