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Firmeware original

Jun 30th, 2021
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  1. ; ASSID [acid] Asynchronous Serial SID Interface Device
  2. ; - A 500kbps serial interface for the MOS 6501 SID
  3. ;   senseitg@hotmail.com
  4.  
  5. ; Designed for MPASM
  6.  
  7. ; To attain the highest possible speed, the SID is driven by a timer
  8. ; set up to generate the 1MHz signal to the SID. Since the SID requires
  9. ; that read/write operations are aligned to the clock, the code loop is
  10. ; designed to always run an exact multiple of clock cycles thus keeping
  11. ; the code synchronized to the timer output.
  12.  
  13.     list            p=16f886
  14.     radix           dec
  15.     #include        p16f886.inc
  16.  
  17. ; Configuration bits
  18. ;   INTOSCIO  - allows power up without 12MHz clock from FTDI
  19. ;   WTD_OFF   - watchdog is not kicked by code
  20. ;   MCLRE_OFF - else will require jumper on programming header
  21. ;   LVP_OFF   - frees up RB3 which is very much required
  22.     __CONFIG _CONFIG1, _INTOSCIO & _WDT_OFF & _MCLRE_OFF & _LVP_OFF
  23.  
  24. SID_CTL     EQU     PORTC           ;SID bus control port
  25. SID_ADDR    EQU     PORTA           ;SID bus address port
  26. SID_DATA    EQU     PORTB           ;SID bus data port
  27. SID_DDR     EQU     TRISB           ;SID bus data direction
  28.  
  29. CTL_LED     EQU     3
  30.  
  31. CTL_CLK     EQU     2               ;SID Ø2  on SID_CTL
  32. CTL_RW      EQU     1               ;SID R/W on SID_CTL
  33. CTL_CS      EQU     0               ;SID CS  on SID_CTL
  34.  
  35. ADDR_SYN    EQU     7               ;SYN     on SID_ADDR
  36. ADDR_DDR    EQU     6               ;DDR     on SID_ADDR
  37. ADDR_RST    EQU     5               ;SID RST on SID_ADDR
  38.  
  39. TEMP        EQU     0x70            ;Temp memory
  40.     ORG 0
  41.    
  42.     GOTO    __INIT
  43.  
  44.     ORG 4
  45. __ISR
  46.     RETFIE
  47.  
  48. __INIT
  49.  
  50.  
  51.     BTFSC   INTCON,     GIE
  52.  
  53.     ;Disable analog
  54.     BSF     STATUS,     RP0
  55.     BSF     STATUS,     RP1
  56.     CLRF    ANSEL                   ;ANSEL   <- 0b00000000
  57.     CLRF    ANSELH                  ;ANSELH  <- 0b00000000
  58.  
  59.     ;Preset data
  60.     BCF     STATUS,     RP0
  61.     BCF     STATUS,     RP1
  62.     CLRF    PORTA                   ;PORTA   <- 0b00000000
  63.     CLRF    PORTB                   ;PORTB   <- 0b00000000
  64.     MOVLW   0x01
  65.     MOVWF   PORTC                   ;PORTC   <- 0b00000001
  66.  
  67.     ;Enable outputs
  68.     BSF     STATUS,     RP0
  69.     MOVLW   0xC0
  70.     MOVWF   TRISA                   ;TRISA   <- 0b11000000: <0:4>:address <5>:rst
  71.     MOVLW   0xFF
  72.     MOVWF   TRISB                   ;TRISB   <- 0b11111111: <0:7>:data
  73.     MOVLW   0xB0
  74.     MOVWF   TRISC                   ;TRISC   <- 0b10110000: <0>:cs <1>:rw <2>:clk <3> led <6>:tx <7>:rx
  75.    
  76.     ;Set up T1/PWM output (SID_CLK)
  77.     MOVLW   0x77
  78.     MOVWF   OSCCON                  ;Switch to 8MHz
  79.  
  80.     MOVLW   0x04
  81.     BCF     STATUS,     RP0
  82.     MOVWF   T2CON                   ;T2CON   <- 0b00000100: T2 = sysclk
  83.     MOVLW   0x01
  84.     BSF     STATUS,     RP0
  85.     MOVWF   PR2                     ;PR2     <- 0b00000001: reload at 1 = 2 cycles
  86.     MOVLW   0x01
  87.     BCF     STATUS,     RP0
  88.     MOVWF   CCPR1L                  ;CCPR1L  <- 0b00000001: pwm duty 50%
  89.     MOVLW   0x0F
  90.     MOVWF   CCP1CON                 ;CCP1CON <- 0b00001111: pwm enable @P1A/SID_CLK
  91.  
  92.     ;UART setup
  93.     BSF     STATUS,     RP0
  94.     BSF     STATUS,     RP1
  95.     MOVLW   0x48
  96.     MOVWF   BAUDCTL                 ;BAUDCTL <- 0b01001000: Use 16bit BRG
  97.     BCF     STATUS,     RP1
  98.     ;CLRF   SPBRG                   ;SPBRG   <- 0b00000000: 2000kbps @ 8Mhz
  99.     MOVLW   3                      
  100.     MOVWF   SPBRG                   ;SPBRG   <- 0b00000011: 500kbps @ 8Mhz
  101.     MOVLW   0x24                   
  102.     MOVWF   TXSTA                   ;TXSTA   <- 0b00100100: Enable transmitter
  103.     BCF     STATUS,     RP0
  104.     MOVLW   0x90
  105.     MOVWF   RCSTA                   ;RCSTA   <- 0b10010000: Enable receiver
  106.  
  107.     NOP
  108.  
  109. __MAIN
  110.     ;@00:0 Wait for data
  111. wait_for_address
  112.     NOP
  113.     BTFSS   PIR1,       RCIF
  114.     GOTO    wait_for_address
  115.     NOP
  116.  
  117.     ;@04:0 Copy received byte to address port
  118.     MOVF    RCREG,      W
  119.     MOVWF   PORTA
  120.  
  121.     ;@06:2 Ensure sync bit set - helps fix sync errors
  122.     MOVWF   TEMP
  123.     BTFSS   TEMP,       ADDR_SYN
  124.     GOTO    wait_for_address
  125.  
  126.     ;@12:0 Requesting read or write?
  127.     BTFSC   TEMP,       ADDR_DDR
  128.     GOTO    __WRITE_REGISTER
  129.  
  130. __READ_REGISTER
  131.  
  132.     ;@14:2 Set data port to input
  133.     BSF     STATUS,     RP0
  134.     MOVLW   0xFF
  135.     MOVWF   SID_DDR
  136.     BCF     STATUS,     RP0
  137.  
  138.     ;@18:2 Pre-align
  139.     NOP
  140.  
  141.     ;@18:2 SID transfer
  142.     BSF     SID_CTL,    CTL_RW
  143.     BCF     SID_CTL,    CTL_CS
  144.     MOVF    SID_DATA,   W
  145.     BSF     SID_CTL,    CTL_CS
  146.  
  147.     ;@23:3 Send
  148.     MOVWF   TXREG
  149.  
  150.     ;@24:0 Post-align
  151.     NOP
  152.  
  153.     ;@26:2
  154.     GOTO    __MAIN
  155.  
  156. __WRITE_REGISTER
  157.  
  158.     BSF     SID_CTL,    CTL_LED
  159.  
  160.     ;@15:3 Wait for data byte
  161. wait_for_data
  162.     NOP
  163.     BTFSS   PIR1,       RCIF
  164.     GOTO    wait_for_data
  165.  
  166.     ;@18:2 Set data port to output
  167.     BSF     STATUS,     RP0
  168.     CLRF    SID_DDR
  169.     BCF     STATUS,     RP0
  170.    
  171.     ;@21:1 Copy received byte to data port
  172.     MOVF    RCREG,      W
  173.     MOVWF   PORTB
  174.  
  175.     ;@23:3 Pre-align
  176.  
  177.     ;@23:3 SID transfer
  178.     BCF     SID_CTL,    CTL_RW
  179.     BCF     SID_CTL,    CTL_CS
  180.     NOP
  181.     BSF     SID_CTL,    CTL_CS
  182.  
  183.     BCF     SID_CTL,    CTL_LED
  184.  
  185.     ;@27:3 Post-align
  186.  
  187.     ;@30:2
  188.     GOTO    __MAIN
  189.  
  190. __END
  191.     END
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