entity ext is
    port
    (
        a, b        : in std_logic_vector(3 downto 0);
        x,y,z       : in std_logic;
        ia,ib,cin   : out std_logic_vector(3 downto 0)
    );
end ext;

architecture fluxo_dados of ext is
begin
    ia(0) <= (not(x) and a(0)) or (x and y and z and not(a(0)));
    ia(1) <= (not(x) and a(1)) or (x and y and z and not(a(1)));
    ia(2) <= (not(x) and a(2)) or (x and y and z and not(a(2)));
    ia(3) <= (not(x) and a(3)) or (x and y and z and not(a(3)));
    ib(0) <= (not(x) and not(y) and not(z) and b(0)) or (not(x) and not(y) and z and not(b(0)));
    ib(1) <= (not(x) and not(y) and not(z) and b(1)) or (not(x) and not(y) and z and not(b(1)));
    ib(2) <= (not(x) and not(y) and not(z) and b(2)) or (not(x) and not(y) and z and not(b(2)));
    ib(3) <= (not(x) and not(y) and not(z) and b(3)) or (not(x) and not(y) and z and not(b(3)));
    cin(0) <= (y and not(z) and not(a(0)) and b(0)) or (x and not(y) and a(0) and b(0)) or (not(x) and y and not(z)) or (not(x) and not(y) and z) or (not(y) and z and b(0)) or (not (y) and z and a(0)) or (y and not(z) and a(0) and not(b(0)));
    cin(1) <= (x and y and not(z) and not(a(1)) and b(1)) or (x and y and not(z) and a(1) and not(b(1))) or (x and not(y) and z and b(1)) or (x and not (y) and z and a(1)) or (x and not (y) and a(1) and b(1));
    cin(2) <= (x and y and not(z) and not(a(2)) and b(2)) or (x and y and not(z) and a(2) and not(b(2))) or (x and not(y) and z and b(2)) or (x and not (y) and z and a(2)) or (x and not (y) and a(2) and b(2));
    cin(3) <= (x and y and not(z) and not(a(3)) and b(3)) or (x and y and not(z) and a(3) and not(b(3))) or (x and not(y) and z and b(3)) or (x and not (y) and z and a(3)) or (x and not (y) and a(3) and b(3));
end fluxo_dados;