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Nov 6th, 2016
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  1. (RECOMPUTE) * INTERLACED *
  2. (RECOMPUTE) * LINEDOUBLER *
  3. * UNHANDLED CASE: READ REGISTER 50..55 with INDIRECT_REGISTER $00 and OFFSET $00 *
  4. (RECOMPUTE) * INTERLACED *
  5. (RECOMPUTE) * LINEDOUBLER *
  6.  
  7. * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
  8. * :upd7201:chaA 03 <- 00 Receiver disable (D0 == 0)
  9. * :upd7201:chaA 05 <- 00 Transmitter disable (D3 == 0)
  10. * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
  11. * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
  12. Repeated for channel B
  13. Repeated 2 times
  14.  
  15. (RECOMPUTE) * INTERLACED *
  16. (RECOMPUTE) * LINEDOUBLER *
  17. - CLOCK BIT: 00
  18.  
  19. * :upd7201:chaB 00 <- 18 Channel Reset command (011b)
  20. * :upd7201:chbB 04 <- 4d Odd Parity enabled, Async mode 2 stop bits, 16x clock
  21. * :upd7201:chbB 03 <- 41 Receiver enabled, 7 bit
  22. * :upd7201:chbB 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
  23. * :upd7201:chbB 02 <- 00 No DMA, Non vectored interrupts D4 D3 D2, p10=RTSB
  24.  
  25. * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
  26. * :upd7201:chaA 02 <- 10 Interrupt vector
  27. * :upd7201:chaA 04 <- 45 Odd Parity enabled, Async mode 1 stop bit, 16x clock rate
  28. * :upd7201:chaA 03 <- 41 Receiver enabled, 7 bit
  29. * :upd7201:chaA 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
  30.  
  31. (RECOMPUTE) * INTERLACED *
  32. (RECOMPUTE) * LINEDOUBLER *
  33.  
  34. * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
  35. * :upd7201:chaA 03 <- 00 Receiver disable (D0 == 0)
  36. * :upd7201:chaA 05 <- 00 Transmitter disable (D3 == 0)
  37. * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
  38. * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
  39. Repeated for channel B
  40.  
  41. (RECOMPUTE) * INTERLACED *
  42. (RECOMPUTE) * LINEDOUBLER *
  43. (RECOMPUTE) FREQUENCY: 600f to COMM.CONTROL REGISTER
  44.  
  45. * :upd7201:chbB 04 <- 10 x32 Clock, Synchronous mode
  46. * :upd7201:chbB 01 <- 18 Interrupt + DMA on received character
  47. * :upd7201:chbB 02 <- 00 No DMA
  48. * :upd7201:chbB 03 <- c0 Receiver disabled, 8 bit
  49. * :upd7201:chbB 05 <- 00 Transmitter disabled
  50. * :upd7201:chbB 06 <- cf Sync byte 1
  51. * :upd7201:chbB 07 <- f3 Sync byte 2
  52.  
  53. (RECOMPUTE) * INTERLACED *
  54. (RECOMPUTE) * LINEDOUBLER *
  55.  
  56. * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
  57. * :upd7201:chaA 03 <- 00 Receiver disable (D0 == 0)
  58. * :upd7201:chaA 05 <- 00 Transmitter disable (D3 == 0)
  59. * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
  60. * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
  61. Repeated for Channel B
  62.  
  63. (RECOMPUTE) * INTERLACED *
  64. (RECOMPUTE) * LINEDOUBLER *
  65. - CLOCK BIT: 00
  66.  
  67. * :upd7201:chaB 00 <- 18 Channel Reset command (011b)
  68. * :upd7201:chbB 04 <- 4d Odd Parity enabled, Async mode 2 stop bits, 16x clock
  69. * :upd7201:chbB 03 <- 41 Receiver enabled, 7 bit
  70. * :upd7201:chbB 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
  71. * :upd7201:chbB 02 <- 00 No DMA, Non vectored interrupts D4 D3 D2, p10=RTSB
  72.  
  73. * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
  74. * :upd7201:chaA 02 <- 10 Interrupt vector
  75. * :upd7201:chaA 04 <- 45 Odd Parity enabled, Async mode 1 stop bit, 16x clock rate
  76. * :upd7201:chaA 03 <- 41 Receiver enabled, 7 bit
  77. * :upd7201:chaA 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
  78.  
  79. * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
  80. * :upd7201:chaA 03 <- 00 Receiver disable (D0 == 0)
  81. * :upd7201:chaA 05 <- 00 Transmitter disable (D3 == 0)
  82. * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
  83. * :upd7201:chaA 00 <- 00 Reg NULL cmd, CRC NULL cmd
  84. Repeated for channel B
  85. Repeated 3 times
  86.  
  87. **** COMM HANDLER INSTALLED ****
  88. * :upd7201:chbB 00 <- 18
  89. * :upd7201:chaA 00 <- 18
  90.  
  91. **** COMM HANDLER INSTALLED ****
  92. * :upd7201:chbB 00 <- 18
  93. * :upd7201:chaA 00 <- 18
  94.  
  95. **** COMM HANDLER INSTALLED ****
  96. * :upd7201:chbB 00 <- 18
  97. * :upd7201:chaA 00 <- 18
  98.  
  99. (RECOMPUTE) * INTERLACED *
  100. (RECOMPUTE) * LINEDOUBLER *
  101. (RECOMPUTE) FREQUENCY: 60
  102.  
  103. * :upd7201:chaB 00 <- 18 Channel Reset command (011b)
  104. * :upd7201:chbB 04 <- 4d Odd Parity enabled, Async mode 2 stop bits, 16x clock
  105. * :upd7201:chbB 03 <- 41 Receiver enabled, 7 bit
  106. * :upd7201:chbB 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
  107. * :upd7201:chbB 02 <- 00 No DMA, Non vectored interrupts D4 D3 D2, p10=RTSB
  108.  
  109. - CLOCK BIT: 00
  110. * :upd7201:chaB 00 <- 18 Channel Reset command (011b)
  111. * :upd7201:chbB 04 <- 4d Odd Parity enabled, Async mode 2 stop bits, 16x clock
  112. * :upd7201:chbB 03 <- 41 Receiver enabled, 7 bit
  113. * :upd7201:chbB 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
  114. * :upd7201:chbB 02 <- 00 No DMA, Non vectored interrupts D4 D3 D2, p10=RTSB
  115.  
  116. * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
  117. * :upd7201:chaA 02 <- 10 Interrupt vector
  118. * :upd7201:chaA 04 <- 45 Odd Parity enabled, Async mode 1 stop bit, 16x clock rate
  119. * :upd7201:chaA 03 <- 41 Receiver enabled, 7 bit
  120. * :upd7201:chaA 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
  121.  
  122. - CLOCK BIT: 00
  123. * :upd7201:chaB 00 <- 18 Channel Reset command (011b)
  124. * :upd7201:chbB 04 <- 4d Odd Parity enabled, Async mode 2 stop bits, 16x clock
  125. * :upd7201:chbB 03 <- 41 Receiver enabled, 7 bit
  126. * :upd7201:chbB 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
  127. * :upd7201:chbB 01 <- 15 Interrupt on received character, Ext Status, status affect vector
  128. * :upd7201:chbB 02 <- 00 No DMA, Non vectored interrupts D4 D3 D2, p10=RTSB
  129.  
  130. * :upd7201:chaA 00 <- 18 Channel Reset command (011b)
  131. * :upd7201:chaA 02 <- 10 Interrupt vector
  132. * :upd7201:chaA 04 <- 45 Odd Parity enabled, Async mode 1 stop bit, 16x clock rate
  133. * :upd7201:chaA 03 <- 41 Receiver enabled, 7 bit
  134. * :upd7201:chaA 05 <- 28 Transmitter enabled, 7 bit, DTR inactive
  135. * :upd7201:chaA 01 <- 10 Interrupt on received character
  136.  
  137. ff to COMM.CONTROL REGISTER
  138.  
  139. * :upd7201:chaA 00 <- 01
  140. * :upd7201:chaA 00 <- 01
  141. * :upd7201:chaA 00 <- 01
  142. * :upd7201:chaA 00 <- 01
  143. * :upd7201:chaA 00 <- 01
  144. * :upd7201:chaA 00 <- 01
  145. * :upd7201:chaA 00 <- 01
  146. * :upd7201:chaA 00 <- 01
  147. * :upd7201:chaA 00 <- 01
  148. * :upd7201:chaA 00 <- 01
  149. * :upd7201:chaA 00 <- 01
  150. * :upd7201:chaA 00 <- 01
  151. * :upd7201:chaA 00 <- 01
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