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- typedef enum logic[1:0]{ A=2'b00, B=2'b01, C=2'b10 } state_t;
- module next_state(input logic a,in2, input state_t cs, output state_t ns);
- always_comb begin
- if(in2)
- ns = A;
- else if(cs == A)
- begin
- if (a== 0) ns = A;
- else ns = B;
- end
- else if (cs == B)
- if (a == 0) ns = C;
- else ns = B;
- else if (cs == C) ns =A;
- else ns = cs;
- end
- endmodule
- module d_flipflop (input logic d, clk, output logic q);
- always_ff @(posedge clk) begin
- q <= d;
- end
- endmodule
- module fsm (input logic in,res, clk, output logic out);
- state_t cs, ns;
- // Connect modules
- next_state nxt ( .a(in),.in2(res), .cs(cs), .ns(ns));
- d_flipflop b0 ( .d(ns[0]), .clk(clk), .q(cs[0]) );
- d_flipflop b1 ( .d(ns[1]), .clk(clk), .q(cs[1]) );
- //gen_output out_comb ( .cs(cs), .o(out) );
- endmodule
- module top;
- logic fsm_in, fsm_out, clk, res;
- //initial begin
- //$dumpfile("dump.vcd");
- //$dumpvars(1);
- //end
- fsm fsm1( .in(fsm_in), .out(fsm_out), .clk(clk), .res(res) );
- endmodule
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