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  1. REGRESS_OPTIONS {
  2. -directed=1
  3. -rocket_run_args =+ " +QDSP6_AXIM2_PRESENT=1 +AXIM2_LOWER_ADDR=0x30000000 +AXIM2_UPPER_ADDR=0x40000000"
  4. -rocket_run_args =+ " +maxTime=1000000 +disableAllIntDrivers=1 +disableL2DirtyEntryCheck=1"
  5. -rocket_run_args =+ " +enableVregPreload=2 +enableQregPreload=2"
  6. -rocket_run_args =+ " +clkRandomEnable=0 +clkTypPeriod_CORE_CLK=1000 +clkTypPeriod_AXIM_CLK=1000 +clkTypPeriod_AXIS_CLK=1000 +clkTypPeriod_AHBM_CLK=1000"
  7. -rocket_run_args =+ " +clkTypPeriod_VPE_ASYNC_CLK=1000"
  8. -rocket_run_args =+ " +randomizeSTID=0"
  9. # Adding option to allow NMI exception
  10. -rocket_run_args =+ " +allow_nmi_exception=1 "
  11. # Adding option to true sharing limited to a single register
  12. -rocket_run_args =+ "+enableReferenceCheckTrust=T0:R2,T1:R2,T2:R2,T3:R2,T4:R2,T5:R2"
  13. -rocket_run_args =+ " +pktidMonitor=1 +schedStallMonitor=1 +set_log_level=trace +max_error=5"
  14. -postgen = "echo QDSP6_WS_TAG=$QDSP6_WS_TAG; $WORKSPACE/verif/core/sim/scripts/perf/get_wave_args.py wave_start 1 wave_stop 1"
  15. -prereport = "$WORKSPACE/verif/core/sim/scripts/perf/get_perf_result.py"
  16. }
  17.    
  18. with open (file_path,'r') as file:
  19.  
  20.     next(file) for 16 times
  21.     lines=file.readlines()
  22.    
  23. with open (file_path,'r') as file:
  24.    content = file.readlines()
  25.    content = [l.strip() for l in content if l.strip()]
  26.  
  27. for line in content[16:]:     # slice through 16 lines
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