module dut(ch0,ch1,ch2,ch3,clk,reset,in);
  input[33:0] in;
  input clk, reset;

  output[33:0] ch0,ch1,ch2,ch3;
  reg[33:0] ch0,ch1,ch2,ch3;
  reg msb;
  reg[1:0] chanal;
  reg[7:0] n;
  reg[19:0] addr;
  reg p;
  reg notXor;
  integer i;
  always @(posedge clk) begin

    if(reset == 1) begin
      ch0 = {1'b0,32'b10101010101010101010101010101010};
      ch1 = {1'b0,32'b10101010101010101010101010101010};
      ch2 = {1'b0,32'b10101010101010101010101010101010};
      ch3 = {1'b0,32'b10101010101010101010101010101010};
    end

    msb = in[33];
    if(msb == 1) begin
      chanal = in[32:31];
      n = in[30:23];
      if(chanal == 2'b00)
        ch0 = in;
      if(chanal == 2'b01)
        ch1 = in;
      if(chanal == 2'b10)
        ch2 = in;
      if(chanal == 2'b11)
        ch3 = in;
    end
    else begin
      notXor = in[33];
      for(i=32;i>0;i=i-1)
        notXor = ~(notXor ^ in[i]);

    end
  end

endmodule

module testRTL();
  reg[33:0] in;
  reg clk, reset;

  wire[33:0] ch0,ch1,ch2,ch3;

  integer i;

  initial begin
    clk = 0;
    forever
      #5 clk = ~clk;
  end

  initial begin
    reset = 1;
    #5 reset = 0;

    for(i=0;i<34;i=1+1)
      in[i] = 1;

  end

  dut test1(ch0,ch1,ch2,ch3,clk,reset,in);
endmodule