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  1. /***************************************************************************
  2.  *             __________               __   ___.
  3.  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
  4.  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
  5.  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
  6.  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
  7.  *                     \/            \/     \/    \/            \/
  8.  * $Id$
  9.  *
  10.  * Copyright (C) 2006 Daniel Ankers
  11.  * Copyright © 2008-2009 Rafaël Carré
  12.  *
  13.  * This program is free software; you can redistribute it and/or
  14.  * modify it under the terms of the GNU General Public License
  15.  * as published by the Free Software Foundation; either version 2
  16.  * of the License, or (at your option) any later version.
  17.  *
  18.  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19.  * KIND, either express or implied.
  20.  *
  21.  ****************************************************************************/
  22.  
  23. #include "config.h" /* for HAVE_MULTIVOLUME */
  24. #include "fat.h"
  25. #include "thread.h"
  26. #include "gcc_extensions.h"
  27. #include "led.h"
  28. #include "sdmmc.h"
  29. #include "system.h"
  30. #include "kernel.h"
  31. #include "cpu.h"
  32. #include <stdio.h>
  33. #include <stdlib.h>
  34. #include <string.h>
  35. #include "as3525v2.h"
  36. #include "pl081.h"  /* DMA controller */
  37. #include "dma-target.h" /* DMA request lines */
  38. #include "clock-target.h"
  39. #include "panic.h"
  40. #include "stdbool.h"
  41. #include "ata_idle_notify.h"
  42. #include "sd.h"
  43. #include "usb.h"
  44.  
  45. #ifdef HAVE_HOTSWAP
  46. #include "disk.h"
  47. #endif
  48.  
  49. #include "lcd.h"
  50. #include <stdarg.h>
  51. #include "sysfont.h"
  52.  
  53. #define     INTERNAL_AS3525  0   /* embedded SD card */
  54. #define     SD_SLOT_AS3525   1   /* SD slot if present */
  55.  
  56. /* Clipv2 Clip+ and Fuzev2 OF all occupy the same size */
  57. #define AMS_OF_SIZE 0xf000
  58.  
  59. /* command flags */
  60. #define MCI_NO_RESP     (0<<0)
  61. #define MCI_RESP        (1<<0)
  62. #define MCI_LONG_RESP   (1<<1)
  63. #define MCI_ACMD        (1<<2)
  64.  
  65. /* controller registers */
  66. #define SD_BASE 0xC6070000
  67.  
  68. #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  69.  
  70. #define MCI_CTRL        SD_REG(0x00)
  71.  
  72. /* control bits */
  73. #define CTRL_RESET      (1<<0)
  74. #define FIFO_RESET      (1<<1)
  75. #define DMA_RESET       (1<<2)
  76. #define INT_ENABLE      (1<<4)
  77. #define DMA_ENABLE      (1<<5)
  78. #define READ_WAIT       (1<<6)
  79. #define SEND_IRQ_RESP   (1<<7)
  80. #define ABRT_READ_DATA  (1<<8)
  81. #define SEND_CCSD       (1<<9)
  82. #define SEND_AS_CCSD    (1<<10)
  83. #define EN_OD_PULLUP    (1<<24)
  84.  
  85.  
  86. #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  87.  
  88. #define PWR_CRD_0       (1<<0)
  89. #define PWR_CRD_1       (1<<1)
  90. #define PWR_CRD_2       (1<<2)
  91. #define PWR_CRD_3       (1<<3)
  92.  
  93. #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  94. /* CLK_DIV_0 :    bits 7:0
  95.  * CLK_DIV_1 :    bits 15:8
  96.  * CLK_DIV_2 :    bits 23:16
  97.  * CLK_DIV_3 :    bits 31:24
  98.  */
  99.  
  100. #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
  101. /* CLK_SRC_CRD0:  bits 1:0
  102.  * CLK_SRC_CRD1:  bits 3:2
  103.  * CLK_SRC_CRD2:  bits 5:4
  104.  * CLK_SRC_CRD3:  bits 7:6
  105.  */
  106.  
  107. #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
  108.  
  109. #define CCLK_ENA_CRD0   (1<<0)
  110. #define CCLK_ENA_CRD1   (1<<1)
  111. #define CCLK_ENA_CRD2   (1<<2)
  112. #define CCLK_ENA_CRD3   (1<<3)
  113. #define CCLK_LP_CRD0    (1<<16)         /* LP --> Low Power Mode? */
  114. #define CCLK_LP_CRD1    (1<<17)
  115. #define CCLK_LP_CRD2    (1<<18)
  116. #define CCLK_LP_CRD3    (1<<19)
  117.  
  118. #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
  119. /* response timeout bits 0:7
  120.  * data timeout bits     8:31
  121.  */
  122.  
  123. #define MCI_CTYPE       SD_REG(0x18)    /* card type */
  124.                                         /* 1 bit per card, set = wide bus */
  125. #define WIDTH4_CRD0     (1<<0)
  126. #define WIDTH4_CRD1     (1<<1)
  127. #define WIDTH4_CRD2     (1<<2)
  128. #define WIDTH4_CRD3     (1<<3)
  129.  
  130. #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size  bits 0:15*/
  131. #define MCI_BYTCNT      SD_REG(0x20)    /* byte count  bits 0:31*/
  132. #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
  133.  
  134.  
  135.  
  136. #define MCI_ARGUMENT    SD_REG(0x28)
  137. #define MCI_COMMAND     SD_REG(0x2C)
  138.  
  139. /* command bits (bits 5:0 are the command index) */
  140. #define CMD_RESP_EXP_BIT        (1<<6)
  141. #define CMD_RESP_LENGTH_BIT     (1<<7)
  142. #define CMD_CHECK_CRC_BIT       (1<<8)
  143. #define CMD_DATA_EXP_BIT        (1<<9)
  144. #define CMD_RW_BIT              (1<<10)
  145. #define CMD_TRANSMODE_BIT       (1<<11)
  146. #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
  147. #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
  148. #define CMD_ABRT_CMD_BIT        (1<<14)
  149. #define CMD_SEND_INIT_BIT       (1<<15)
  150. #define CMD_CARD_NO(x)          ((x)<<16)         /* 5 bits wide  */
  151. #define CMD_SEND_CLK_ONLY       (1<<21)
  152. #define CMD_READ_CEATA          (1<<22)
  153. #define CMD_CCS_EXPECTED        (1<<23)
  154. #define CMD_DONE_BIT            (1<<31)
  155.  
  156. #define TRANSFER_CMD  (cmd == SD_READ_MULTIPLE_BLOCK ||   \
  157.                        cmd == SD_WRITE_MULTIPLE_BLOCK)
  158.  
  159. #define MCI_RESP0       SD_REG(0x30)
  160. #define MCI_RESP1       SD_REG(0x34)
  161. #define MCI_RESP2       SD_REG(0x38)
  162. #define MCI_RESP3       SD_REG(0x3C)
  163.  
  164. #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
  165. #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
  166.                                          * status clear */
  167.  
  168. /* interrupt bits */                /* C D E   (Cmd) (Data) (End) */
  169. #define MCI_INT_CRDDET  (1<<0)      /*          card detect */
  170. #define MCI_INT_RE      (1<<1)      /* x         response error */
  171. #define MCI_INT_CD      (1<<2)      /*     x     command done */
  172. #define MCI_INT_DTO     (1<<3)      /*     x     data transfer over */
  173. #define MCI_INT_TXDR    (1<<4)      /*          tx fifo data request */
  174. #define MCI_INT_RXDR    (1<<5)      /*          rx fifo data request */
  175. #define MCI_INT_RCRC    (1<<6)      /* x         response crc error */
  176. #define MCI_INT_DCRC    (1<<7)      /*   x       data crc error */
  177. #define MCI_INT_RTO     (1<<8)      /* x         response timeout */
  178. #define MCI_INT_DRTO    (1<<9)      /*   x       data read timeout */
  179. #define MCI_INT_HTO     (1<<10)     /*   x       data starv timeout */
  180. #define MCI_INT_FRUN    (1<<11)     /*   x       fifo over/underrun */
  181. #define MCI_INT_HLE     (1<<12)     /* x x        hw locked while error */
  182. #define MCI_INT_SBE     (1<<13)     /*   x       start bit error */
  183. #define MCI_INT_ACD     (1<<14)     /*          auto command done */
  184. #define MCI_INT_EBE     (1<<15)     /*   x       end bit error */
  185. #define MCI_INT_SDIO    (0xf<<16)
  186.  
  187. /*
  188.  *  STATUS register
  189.  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
  190.  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
  191.  *  & 8         = MCI_INT_DTO
  192.  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
  193.  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
  194.  */
  195.  
  196. #define MCI_CMD_ERROR    \
  197.          (MCI_INT_RE   | \
  198.           MCI_INT_RCRC | \
  199.           MCI_INT_RTO  | \
  200.           MCI_INT_HLE)
  201.  
  202. #define MCI_DATA_ERROR    \
  203.         ( MCI_INT_DCRC  | \
  204.           MCI_INT_DRTO  | \
  205.           MCI_INT_HTO   | \
  206.           MCI_INT_FRUN  | \
  207.           MCI_INT_HLE   | \
  208.           MCI_INT_SBE   | \
  209.           MCI_INT_EBE)
  210.  
  211. #define MCI_STATUS      SD_REG(0x48)
  212.  
  213. #define FIFO_RX_WM              (1<<0)
  214. #define FIFO_TX_WM              (1<<1)
  215. #define FIFO_EMPTY              (1<<2)
  216. #define FIFO_FULL               (1<<3)
  217. #define CMD_FSM_STATE_B0        (1<<4)
  218. #define CMD_FSM_STATE_B1        (1<<5)
  219. #define CMD_FSM_STATE_B2        (1<<6)
  220. #define CMD_FSM_STATE_B3        (1<<7)
  221. #define DATA_3_STAT             (1<<8)
  222. #define DATA_BUSY               (1<<9)
  223. #define DATA_STAT_MC_BUSY       (1<<10)
  224. #define RESP_IDX_B0             (1<<11)
  225. #define RESP_IDX_B1             (1<<12)
  226. #define RESP_IDX_B2             (1<<13)
  227. #define RESP_IDX_B3             (1<<14)
  228. #define RESP_IDX_B4             (1<<15)
  229. #define RESP_IDX_B5             (1<<16)
  230. #define FIFO_CNT_B00            (1<<17)
  231. #define FIFO_CNT_B01            (1<<18)
  232. #define FIFO_CNT_B02            (1<<19)
  233. #define FIFO_CNT_B03            (1<<20)
  234. #define FIFO_CNT_B04            (1<<21)
  235. #define FIFO_CNT_B05            (1<<22)
  236. #define FIFO_CNT_B06            (1<<23)
  237. #define FIFO_CNT_B07            (1<<24)
  238. #define FIFO_CNT_B08            (1<<25)
  239. #define FIFO_CNT_B09            (1<<26)
  240. #define FIFO_CNT_B10            (1<<27)
  241. #define FIFO_CNT_B11            (1<<28)
  242. #define FIFO_CNT_B12            (1<<29)
  243. #define DMA_ACK                 (1<<30)
  244. #define START_CMD               (1<<31)
  245.  
  246. #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
  247. /* TX watermark :    bits 11:0
  248.  * RX watermark :    bits 27:16
  249.  * DMA MTRANS SIZE : bits 30:28
  250.  * bits 31, 15:12 : unused
  251.  */
  252. #define MCI_FIFOTH_MASK 0x8000f000
  253.  
  254. #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
  255.  
  256. #define CDETECT_CRD_0   (1<<0)
  257. #define CDETECT_CRD_1   (1<<1)
  258. #define CDETECT_CRD_2   (1<<2)
  259. #define CDETECT_CRD_3   (1<<3)
  260.  
  261. #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
  262. #define MCI_GPIO        SD_REG(0x58)
  263. #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count (card)*/
  264. #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes (FIFO)*/
  265. #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce  bits 23:0*/
  266. #define MCI_USRID       SD_REG(0x68)    /* user id */
  267. #define MCI_VERID       SD_REG(0x6C)    /* version id */
  268.  
  269. #define MCI_HCON        SD_REG(0x70)    /* hardware config */
  270. /* bit  0       : card type
  271.  * bits 5:1     : maximum card index
  272.  * bit  6       : BUS TYPE
  273.  * bits 9:7     : DATA WIDTH
  274.  * bits 15:10   : ADDR WIDTH
  275.  * bits 17:16   : DMA IF
  276.  * bits 20:18   : DMA WIDTH
  277.  * bit  21      : FIFO RAM INSIDE
  278.  * bit  22      : IMPL HOLD REG
  279.  * bit  23      : SET CLK FALSE
  280.  * bits 25:24   : MAX CLK DIV IDX
  281.  * bit  26      : AREA OPTIM
  282.  */
  283.  
  284. #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
  285. /* bit  0       : SWR
  286.  * bit  1       : FB
  287.  * bits 6:2     : DSL
  288.  * bit  7       : DE
  289.  * bit  10:8    : PBL
  290.  */
  291.  
  292. #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
  293. #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
  294. #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
  295. /* bit  0       : TI
  296.  * bit  1       : RI
  297.  * bit  2       : FBE
  298.  * bit  3       : unused
  299.  * bit  4       : DU
  300.  * bit  5       : CES
  301.  * bits 7:6     : unused
  302.  * bits 8       : NIS
  303.  * bit  9       : AIS
  304.  * bits 12:10   : EB
  305.  * bits 16:13   : FSM
  306.  */
  307.  
  308. #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
  309. /* bit  0       : TI
  310.  * bit  1       : RI
  311.  * bit  2       : FBE
  312.  * bit  3       : unused
  313.  * bit  4       : DU
  314.  * bit  5       : CES
  315.  * bits 7:6     : unused
  316.  * bits 8       : NI
  317.  * bit  9       : AI
  318.  */
  319. #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
  320. #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
  321.  
  322. #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
  323.  
  324. #define UNALIGNED_NUM_SECTORS 10
  325. static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
  326. static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
  327.  
  328. static tCardInfo card_info[NUM_DRIVES];
  329.  
  330. /* for compatibility */
  331. static long last_disk_activity = -1;
  332.  
  333. static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
  334. static const char         sd_thread_name[] = "ata/sd";
  335. static struct mutex       sd_mtx SHAREDBSS_ATTR;
  336. static struct event_queue sd_queue;
  337. #ifndef BOOTLOADER
  338. bool sd_enabled = false;
  339. #endif
  340.  
  341. static struct semaphore transfer_completion_signal;
  342. static struct semaphore command_completion_signal;
  343. static volatile bool retry;
  344. static volatile int cmd_error;
  345.  
  346. #if defined(HAVE_MULTIDRIVE)
  347. #define EXT_SD_BITS (1<<2)
  348. #endif
  349.  
  350. static inline void mci_delay(void) { udelay(1000); }
  351.  
  352. void INT_NAND(void)
  353. {
  354.     MCI_CTRL &= ~INT_ENABLE;
  355.     /* use raw status here as we need to check some Ints that are masked */
  356.     const int status = MCI_RAW_STATUS;
  357.  
  358.     MCI_RAW_STATUS = status;    /* clear status */
  359.  
  360.     if(status & MCI_DATA_ERROR)
  361.         retry = true;
  362.  
  363.     if( status & (MCI_INT_DTO|MCI_DATA_ERROR))
  364.         semaphore_release(&transfer_completion_signal);
  365.  
  366.     cmd_error = status & MCI_CMD_ERROR;
  367.  
  368.     if(status & MCI_INT_CD)
  369.         semaphore_release(&command_completion_signal);
  370.  
  371.     MCI_CTRL |= INT_ENABLE;
  372. }
  373.  
  374. static inline bool card_detect_target(void)
  375. {
  376. #if defined(HAVE_MULTIDRIVE)
  377. #if defined(SANSA_FUZEV2)
  378.     return GPIOA_PIN(2);
  379. #elif defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
  380.     return !(GPIOA_PIN(2));
  381. #else
  382. #error "microSD pin not defined for your target"
  383. #endif
  384. #else
  385.     return false;
  386. #endif
  387. }
  388.  
  389. static bool send_cmd(const int drive, const int cmd, const int arg, const int flags,
  390.         unsigned long *response)
  391. {
  392.     int card_no;
  393.  
  394.     if ((flags & MCI_ACMD) && /* send SD_APP_CMD first */
  395.         !send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, response))
  396.         return false;
  397.  
  398. #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
  399.     if (amsv2_variant == 1)
  400.         GPIOB_PIN(5) = (drive == INTERNAL_AS3525) ? 1 << 5 : 0;
  401. #endif
  402.  
  403.     MCI_ARGUMENT = arg;
  404.  
  405. #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
  406.     if (amsv2_variant == 1)
  407.         card_no = 1 << 16;
  408.     else
  409. #endif
  410.         card_no = CMD_CARD_NO(drive);
  411.  
  412.     /* Construct MCI_COMMAND  */
  413.     MCI_COMMAND =
  414.       /*b5:0*/    cmd
  415.       /*b6  */  | ((flags & MCI_RESP)                ? CMD_RESP_EXP_BIT:      0)
  416.       /*b7  */  | ((flags & MCI_LONG_RESP)           ? CMD_RESP_LENGTH_BIT:   0)
  417.       /*b8      | CMD_CHECK_CRC_BIT       unused  */
  418.       /*b9  */  | (TRANSFER_CMD                      ? CMD_DATA_EXP_BIT:      0)
  419.       /*b10 */  | ((cmd == SD_WRITE_MULTIPLE_BLOCK)  ? CMD_RW_BIT:            0)
  420.       /*b11     | CMD_TRANSMODE_BIT       unused  */
  421.       /*b12     | CMD_SENT_AUTO_STOP_BIT  unused  */
  422.       /*b13 */  | ((cmd != SD_STOP_TRANSMISSION)     ? CMD_WAIT_PRV_DAT_BIT:  0)
  423.       /*b14     | CMD_ABRT_CMD_BIT        unused  */
  424.       /*b15 */  | ((cmd == SD_GO_IDLE_STATE)         ? CMD_SEND_INIT_BIT:     0)
  425.    /*b20:16 */  |                                      card_no
  426.       /*b21     | CMD_SEND_CLK_ONLY       unused  */
  427.       /*b22     | CMD_READ_CEATA          unused  */
  428.       /*b23     | CMD_CCS_EXPECTED        unused  */
  429.       /*b31 */  |                                      CMD_DONE_BIT;
  430.  
  431.     semaphore_wait(&command_completion_signal, TIMEOUT_BLOCK);
  432.  
  433.     /*  Handle command responses & errors */
  434.     if(flags & MCI_RESP)
  435.     {
  436.         if(cmd_error & (MCI_INT_RCRC | MCI_INT_RTO))
  437.             return false;
  438.  
  439.         if(flags & MCI_LONG_RESP)
  440.         {
  441.             response[0] = MCI_RESP3;
  442.             response[1] = MCI_RESP2;
  443.             response[2] = MCI_RESP1;
  444.             response[3] = MCI_RESP0;
  445.         }
  446.         else
  447.             response[0] = MCI_RESP0;
  448.     }
  449.     return true;
  450. }
  451.  
  452. static int sd_wait_for_tran_state(const int drive)
  453. {
  454.     unsigned long response;
  455.     unsigned int timeout = current_tick + 5*HZ;
  456.     int cmd_retry = 10;
  457.     if (drive == INTERNAL_AS3525)
  458.         return 0;
  459.     while (1)
  460.     {
  461.         while (!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP,
  462.                          &response) && cmd_retry > 0)
  463.         {
  464.             cmd_retry--;
  465.         }
  466.  
  467.         if (cmd_retry <= 0)
  468.             return -1;
  469.  
  470.         if (((response >> 9) & 0xf) == SD_TRAN)
  471.             return 0;
  472.  
  473.         if(TIME_AFTER(current_tick, timeout))
  474.             return -10 * ((response >> 9) & 0xf);
  475.  
  476.         last_disk_activity = current_tick;
  477.     }
  478. }
  479.  
  480.  
  481. static int sd_init_card(const int drive)
  482. {
  483.     unsigned long response;
  484.     long init_timeout;
  485.     bool sd_v2 = false;
  486.     if (drive == INTERNAL_AS3525)
  487.         return 0;
  488.     card_info[drive].initialized = 0;
  489.     card_info[drive].rca = 0;
  490.  
  491.     /*  assume 24 MHz clock / 60 = 400 kHz  */
  492.     MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C;    /* CLK_DIV_0 : bits 7:0  */
  493.  
  494.     /* 100 - 400kHz clock required for Identification Mode  */
  495.     /*  Start of Card Identification Mode ************************************/
  496.  
  497.     /* CMD0 Go Idle  */
  498.     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
  499.         return -1;
  500.     mci_delay();
  501.  
  502.     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
  503.       Non v2 cards will not respond to this command*/
  504.     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
  505.         if((response & 0xFFF) == 0x1AA)
  506.             sd_v2 = true;
  507.  
  508.     /* timeout for initialization is 1sec, from SD Specification 2.00 */
  509.     init_timeout = current_tick + HZ;
  510.  
  511.     do {
  512.         /* this timeout is the only valid error for this loop*/
  513.         if(TIME_AFTER(current_tick, init_timeout))
  514.             return -2;
  515.  
  516.          /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
  517.         if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
  518.                         MCI_ACMD|MCI_RESP, &card_info[drive].ocr))
  519.             return -3;
  520.     } while(!(card_info[drive].ocr & (1<<31)) );
  521.  
  522.     /* CMD2 send CID */
  523.     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info[drive].cid))
  524.         return -4;
  525.  
  526.     /* CMD3 send RCA */
  527.     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
  528.         return -5;
  529.  
  530. #ifdef HAVE_MULTIDRIVE
  531.     /* Make sure we have 2 unique rca numbers */
  532.     if(card_info[INTERNAL_AS3525].rca == card_info[SD_SLOT_AS3525].rca)
  533.         if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
  534.             return -6;
  535. #endif
  536.     /*  End of Card Identification Mode   ************************************/
  537.  
  538.     /*  Card back to full speed  */
  539.     MCI_CLKDIV &= ~(0xFF);    /* CLK_DIV_0 : bits 7:0 = 0x00 */
  540.  
  541.     /* CMD9 send CSD */
  542.     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
  543.                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
  544.         return -11;
  545.  
  546.     sd_parse_csd(&card_info[drive]);
  547.  
  548.     if(drive == INTERNAL_AS3525) /* The OF is stored in the first blocks */
  549.         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
  550.  
  551. #ifndef BOOTLOADER
  552.     /*  Switch to to 4 bit widebus mode  */
  553.  
  554.     /*  CMD7 w/rca: Select card to put it in TRAN state */
  555.     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
  556.         return -12;
  557.     if(sd_wait_for_tran_state(drive) < 0)
  558.         return -13;
  559.  
  560.     /* ACMD6: set bus width to 4-bit */
  561.     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_ACMD|MCI_RESP, &response))
  562.         return -15;
  563.     /* ACMD42: disconnect the pull-up resistor on CD/DAT3 */
  564.     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_ACMD|MCI_RESP, &response))
  565.         return -17;
  566.  
  567.     /* Now that card is widebus make controller aware */
  568. #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
  569.     if (amsv2_variant == 1)
  570.         MCI_CTYPE |= 1<<1;
  571.     else
  572. #endif
  573.         MCI_CTYPE |= (1<<drive);
  574.  
  575. #endif /* ! BOOTLOADER */
  576.  
  577.     card_info[drive].initialized = 1;
  578.  
  579.     return 0;
  580. }
  581.  
  582. static void sd_thread(void) NORETURN_ATTR;
  583. static void sd_thread(void)
  584. {
  585.     struct queue_event ev;
  586.     bool idle_notified = false;
  587.  
  588.     while (1)
  589.     {
  590.         queue_wait_w_tmo(&sd_queue, &ev, HZ);
  591.  
  592.         switch ( ev.id )
  593.         {
  594. #ifdef HAVE_HOTSWAP
  595.         case SYS_HOTSWAP_INSERTED:
  596.         case SYS_HOTSWAP_EXTRACTED:;
  597.             int success = 1;
  598.  
  599.             disk_unmount(SD_SLOT_AS3525); /* release "by force" */
  600.  
  601.             mutex_lock(&sd_mtx); /* lock-out card activity */
  602.  
  603.             /* Force card init for new card, re-init for re-inserted one or
  604.              * clear if the last attempt to init failed with an error. */
  605.             card_info[SD_SLOT_AS3525].initialized = 0;
  606.  
  607.             if (ev.id == SYS_HOTSWAP_INSERTED)
  608.             {
  609.                 sd_enable(true);
  610.                 success = sd_init_card(SD_SLOT_AS3525) == 0 ? 2 : 0;
  611.                 sd_enable(false);
  612.             }
  613.  
  614.             mutex_unlock(&sd_mtx);
  615.  
  616.             if (success > 1)
  617.                 success = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
  618.  
  619.             /*
  620.              * Mount succeeded, or this was an EXTRACTED event,
  621.              * in both cases notify the system about the changed filesystems
  622.              */
  623.             if (success)
  624.                 queue_broadcast(SYS_FS_CHANGED, 0);
  625.  
  626.             break;
  627. #endif /* HAVE_HOTSWAP */
  628.  
  629.         case SYS_TIMEOUT:
  630.             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
  631.             {
  632.                 idle_notified = false;
  633.             }
  634.             else if (!idle_notified)
  635.             {
  636.                 call_storage_idle_notifys(false);
  637.                 idle_notified = true;
  638.             }
  639.             break;
  640.  
  641.         case SYS_USB_CONNECTED:
  642.             usb_acknowledge(SYS_USB_CONNECTED_ACK);
  643.             /* Wait until the USB cable is extracted again */
  644.             usb_wait_for_disconnect(&sd_queue);
  645.  
  646.             break;
  647.         }
  648.     }
  649. }
  650.  
  651. static void init_controller(void)
  652. {
  653.     int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
  654.     int card_mask = (1 << hcon_numcards) - 1;
  655.     int pwr_mask;
  656.  
  657. #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
  658.     if (amsv2_variant == 1)
  659.         pwr_mask = 1 << 1;
  660.     else
  661. #endif
  662.         pwr_mask = card_mask;
  663.  
  664.     MCI_PWREN &= ~pwr_mask;             /*  power off all cards  */
  665.     MCI_PWREN = pwr_mask;               /*  power up cards  */
  666.  
  667.     MCI_CTRL |= CTRL_RESET;
  668.     while(MCI_CTRL & CTRL_RESET)
  669.         ;
  670.  
  671.     MCI_RAW_STATUS = 0xffffffff;        /* Clear all MCI Interrupts  */
  672.  
  673.     MCI_TMOUT = 0xffffffff;             /*  data b31:8, response b7:0 */
  674.  
  675.     MCI_CTYPE = 0x0;                    /*  all cards 1 bit bus for now */
  676.  
  677.     MCI_CLKENA = card_mask;             /*  Enables card clocks  */
  678.  
  679.     MCI_ARGUMENT = 0;
  680.     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
  681.     while(MCI_COMMAND & CMD_DONE_BIT)
  682.         ;
  683.  
  684.     MCI_DEBNCE = 0xfffff;               /* default value */
  685.  
  686.     /* Rx watermark = 63(sd reads)  Tx watermark = 128 (sd writes) */
  687.     MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080;
  688.  
  689. /*  RCRC & RTO interrupts should be set together with the CD interrupt but
  690.  *  in practice sometimes incorrectly precede the CD interrupt.  If we leave
  691.  *  them masked for now we can check them in the isr by reading raw status when
  692.  *  the CD int is triggered.
  693.  */
  694.     MCI_MASK |= (MCI_DATA_ERROR | MCI_INT_DTO | MCI_INT_CD);
  695.  
  696.     MCI_CTRL |= INT_ENABLE | DMA_ENABLE;
  697.  
  698.     MCI_BLKSIZ = SD_BLOCK_SIZE;
  699. }
  700.  
  701. int sd_init(void)
  702. {
  703.     int ret;
  704.  
  705.     bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
  706.  
  707.     CGU_SDSLOT = (1<<7)         /* interface enable */
  708.                | (AS3525_SDSLOT_DIV << 2)
  709.                | 1;             /* clock source = PLLA */
  710.  
  711.     semaphore_init(&transfer_completion_signal, 1, 0);
  712.     semaphore_init(&command_completion_signal, 1, 0);
  713.  
  714. #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
  715.     if (amsv2_variant == 1)
  716.         GPIOB_DIR |= 1 << 5;
  717. #endif
  718.  
  719. #ifdef HAVE_MULTIDRIVE
  720.     /* clear previous irq */
  721.     GPIOA_IC = EXT_SD_BITS;
  722.     /* enable edge detecting */
  723.     GPIOA_IS &= ~EXT_SD_BITS;
  724.     /* detect both raising and falling edges */
  725.     GPIOA_IBE |= EXT_SD_BITS;
  726.     /* enable the card detect interrupt */
  727.     GPIOA_IE |= EXT_SD_BITS;
  728. #endif /* HAVE_MULTIDRIVE */
  729.  
  730. #ifndef SANSA_CLIPV2
  731.     /* Configure XPD for SD-MCI interface */
  732.     bitmod32(&CCU_IO, 1<<2, 3<<2);
  733. #endif
  734.  
  735.     VIC_INT_ENABLE = INTERRUPT_NAND;
  736.  
  737.     init_controller();
  738.     ret = sd_init_card(INTERNAL_AS3525);
  739.     if(ret < 0)
  740.         return ret;
  741.  
  742.     /* init mutex */
  743.     mutex_init(&sd_mtx);
  744.  
  745.     queue_init(&sd_queue, true);
  746.     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
  747.             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
  748.  
  749. #ifndef BOOTLOADER
  750.     sd_enabled = true;
  751.     sd_enable(false);
  752. #endif
  753.     return 0;
  754. }
  755.  
  756. static int sd_transfer_sectors(IF_MD(int drive,) unsigned long start,
  757.                                 int count, void* buf, bool write)
  758. {
  759.     unsigned long response;
  760.     int ret = 0;
  761. #ifndef HAVE_MULTIDRIVE
  762.     const int drive = 0;
  763. #endif
  764.     bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
  765.     int retry_all = 2;
  766.     int const retry_data_max = 3;
  767.     int retry_data;
  768.     unsigned int real_numblocks;
  769.  
  770.     mutex_lock(&sd_mtx);
  771. #ifndef BOOTLOADER
  772.     sd_enable(true);
  773.     led(true);
  774. #else
  775.     if (drive == INTERNAL_AS3525)
  776.         goto exit;
  777. #endif
  778.  
  779.  
  780.  
  781.     if(count < 1) /* XXX: why is it signed ? */
  782.     {
  783.         panicf("SD count:%d write:%d drive:%d", count, write, drive);
  784. /*
  785.         ret = -18;
  786.         goto exit;
  787. */
  788.     }
  789.  
  790.     /* skip SanDisk OF */
  791.     if (drive == INTERNAL_AS3525)
  792.         start += AMS_OF_SIZE;
  793.  
  794.     while (!card_info[drive].initialized)
  795.     {
  796. retry_with_reinit:
  797.         if (--retry_all < 0)
  798.             goto exit;
  799.         ret = sd_init_card(drive);
  800.     }
  801.  
  802.     /* Check the real block size after the card has been initialized */
  803.     real_numblocks = card_info[drive].numblocks;
  804.     /* 'start' represents the real (physical) starting sector
  805.      *  so we must compare it to the real (physical) number of sectors */
  806.     if (drive == INTERNAL_AS3525)
  807.         real_numblocks += AMS_OF_SIZE;
  808.     if ((start+count) > real_numblocks)
  809.     {
  810.         ret = -19;
  811.         goto retry_with_reinit;
  812.     }
  813.  
  814.     /*  CMD7 w/rca: Select card to put it in TRAN state */
  815.     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
  816.     {
  817.         ret = -20;
  818.         goto retry_with_reinit;
  819.     }
  820.  
  821.     dma_retain();
  822.  
  823.     if(aligned)
  824.     {   /* direct transfer, indirect is always uncached */
  825.         if(write)
  826.             commit_dcache_range(buf, count * SECTOR_SIZE);
  827.         else
  828.             discard_dcache_range(buf, count * SECTOR_SIZE);
  829.     }
  830.  
  831.     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
  832.     retry_data = retry_data_max;
  833.  
  834.     while (count > 0)
  835.     {
  836.         void *dma_buf;
  837.         unsigned int transfer = count;
  838.  
  839.         last_disk_activity = current_tick;
  840.  
  841.         if(aligned)
  842.         {
  843.             dma_buf = AS3525_PHYSICAL_ADDR(buf);
  844.         }
  845.         else
  846.         {
  847.             dma_buf = AS3525_PHYSICAL_ADDR(&aligned_buffer[0]);
  848.             if(transfer > UNALIGNED_NUM_SECTORS)
  849.                 transfer = UNALIGNED_NUM_SECTORS;
  850.  
  851.             if(write)
  852.                 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
  853.         }
  854.  
  855.         /* Interrupt handler might set this to true during transfer */
  856.         retry = false;
  857.  
  858.         MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
  859.  
  860.         int arg = start;
  861.         if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
  862.             arg *= SD_BLOCK_SIZE;
  863.  
  864.         if(write)
  865.             dma_enable_channel(1, dma_buf, MCI_FIFO, DMA_PERI_SD,
  866.                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
  867.         else
  868.             dma_enable_channel(1, MCI_FIFO, dma_buf, DMA_PERI_SD,
  869.                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
  870.  
  871.         if(!send_cmd(drive, cmd, arg, MCI_RESP, &response))
  872.         {
  873.             ret = -21;
  874.             break;
  875.         }
  876.  
  877.         semaphore_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
  878.  
  879.         last_disk_activity = current_tick;
  880.  
  881.         if(write)
  882.         {
  883.             /* wait for the card to exit programming state */
  884.             while(MCI_STATUS & DATA_BUSY) ;
  885.         }
  886.  
  887.         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_RESP, &response))
  888.         {
  889.             ret = -22;
  890.             break;
  891.         }
  892.  
  893.         ret = sd_wait_for_tran_state(drive);
  894.         if (ret < 0)
  895.         {
  896.             ret -= 25;
  897.             break;
  898.         }
  899.  
  900.         /* According to datasheet DMA channel should be automatically disabled
  901.          * when transfer completes. But it not true for DMA_PERI_SD.
  902.          * Disable DMA channel manually to prevent problems with DMA. */
  903.         dma_disable_channel(1);
  904.  
  905.         if (retry) /*  reset controller if we had an error  */
  906.         {
  907.             MCI_CTRL |= (FIFO_RESET|DMA_RESET);
  908.             while (MCI_CTRL & (FIFO_RESET|DMA_RESET));
  909.             if (--retry_data >= 0)
  910.                 continue;
  911.  
  912.             ret -= 24;
  913.             break;
  914.         }
  915.  
  916.         if (!write && !aligned)
  917.             memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
  918.         buf += transfer * SD_BLOCK_SIZE;
  919.         start += transfer;
  920.         count -= transfer;
  921.     }
  922.  
  923.     dma_release();
  924.  
  925.     if (ret != 0) /* if we have error */
  926.             goto retry_with_reinit;
  927.  
  928.     /* CMD lines are separate, not common, so we need to actively deselect */
  929.     /*  CMD7 w/rca =0 : deselects card & puts it in STBY state */
  930.     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
  931.         ret = -23;
  932.  
  933. exit:
  934. #ifndef BOOTLOADER
  935.     sd_enable(false);
  936.     led(false);
  937. #endif
  938.     mutex_unlock(&sd_mtx);
  939.     return ret;
  940. }
  941.  
  942. int sd_read_sectors(IF_MD(int drive,) unsigned long start, int count,
  943.                     void* buf)
  944. {
  945.     return sd_transfer_sectors(IF_MD(drive,) start, count, buf, false);
  946. }
  947.  
  948. int sd_write_sectors(IF_MD(int drive,) unsigned long start, int count,
  949.                      const void* buf)
  950. {
  951.     return sd_transfer_sectors(IF_MD(drive,) start, count, (void*)buf, true);
  952. }
  953.  
  954. #ifndef BOOTLOADER
  955. long sd_last_disk_activity(void)
  956. {
  957.     return last_disk_activity;
  958. }
  959.  
  960. void sd_enable(bool on)
  961. {
  962.     if (on)
  963.     {
  964.         bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
  965.         CGU_SDSLOT |= (1<<7);               /* interface enable */
  966.     }
  967.     else
  968.     {
  969.         CGU_SDSLOT &= ~(1<<7);              /* interface enable */
  970.         bitclr32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
  971.     }
  972. }
  973. #endif /* BOOTLOADER */
  974.  
  975. tCardInfo *card_get_info_target(int card_no)
  976. {
  977.     return &card_info[card_no];
  978. }
  979.  
  980. #ifdef HAVE_HOTSWAP
  981. bool sd_removable(IF_MD_NONVOID(int drive))
  982. {
  983.     return (drive == SD_SLOT_AS3525);
  984. }
  985.  
  986. bool sd_present(IF_MD_NONVOID(int drive))
  987. {
  988.     return (drive == INTERNAL_AS3525) ? true : card_detect_target();
  989. }
  990.  
  991. static int sd1_oneshot_callback(struct timeout *tmo)
  992. {
  993.     (void)tmo;
  994.  
  995.     /* This is called only if the state was stable for 300ms - check state
  996.      * and post appropriate event. */
  997.     if (card_detect_target())
  998.     {
  999.         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
  1000.     }
  1001.     else
  1002.         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
  1003.  
  1004.     return 0;
  1005. }
  1006.  
  1007. void sd_gpioa_isr(void)
  1008. {
  1009.     static struct timeout sd1_oneshot;
  1010.  
  1011.     if (GPIOA_MIS & EXT_SD_BITS)
  1012.     {
  1013.         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
  1014.         GPIOA_IC = EXT_SD_BITS; /* acknowledge interrupt */
  1015.     }
  1016. }
  1017. #endif /* HAVE_HOTSWAP */
  1018.  
  1019. #ifdef CONFIG_STORAGE_MULTI
  1020. int sd_num_drives(int first_drive)
  1021. {
  1022.     /* We don't care which logical drive number(s) we have been assigned */
  1023.     (void)first_drive;
  1024.  
  1025.     return NUM_DRIVES;
  1026. }
  1027. #endif /* CONFIG_STORAGE_MULTI */
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