library ieee;
use ieee.std_logic_1164.all;

entity deb is
generic ( N: integer :=400);
port(
    sin, clk : in std_logic;
    output   : out std_logic);
end deb;

architecture arh of deb is
signal brojac, brojac2 : integer range 0 to 1000;
signal flag : std_logic;

begin

    process(clk)
    begin

    if rising_edge(clk) then

        if sin='1' then
            brojac <= 0;
        elsif sin='0' and flag='0' and brojac /= N then
            brojac <= brojac + 1;
        elsif brojac = N then
            flag <= '1';
            brojac <= 0;
        end if;
        if flag='1' then
            brojac2 <= brojac2 + 1;
            output<='1';
        end if;
        if brojac2 = N then
            flag<='0';
            output<='0';
            brojac2<=0;
        end if;

    end if;

    end process;

end arh;