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A) The block size is 64B. 2$^x$ = 64. Solving for x will show that the offset will need 6 bits.
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The number of indices needed are the equal to the number of sets required. The number of sets needed is 16KB/64B/1 = 256 sets. Solving 2$^x$ = 256 will show that the index needs 8 bits.

To get the tag bits, subtract the index and offset bits from the total memory address. 32-6-8 = 18 bits.

The binary string for the memory address is 0000 0000 1111 1111 1011 0000 0100 1000. Converting the address to hexadecimal and using the bits from above, the offset will be 0x8, the index will be 0xc1, and the tag will be 0x003fe.
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B) The block size is 16B, 2$^x$ = 16. Solving for x will show that the offset will need 4 bits.
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The number of indices needed are the equal to the number of sets required. The number of sets needed is 512KB/16B/8 = 4096 sets. Solving 2$^x$ = 4096 will show that the index needs 12 bits.

To get the tag bits, subtract the index and offset bits from the total memory address. 32-4-12 = 16 bits.

The binary string for the memory address is 0001 1010 0010 1011 0011 1100 0100 1101. Converting the address to hexadecimal and using the bits from above, the offset will be 0xd, the index will be 0x3c4, and the tag will be 0x1a2b.
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C) Use the AMAT = t$_h$ + r$_m$ * t$_p$. The AMAT will be 4 + (1-0.75) $*$ (28-4) = 10 cycles
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D) Use the equation stated in part C. Calculating L2 cache AMAT: 10 + (0.5 * 80) = 50 cycles. Calculating overall AMAT by plugging in result from L2 cache AMAT into miss penalty: 2 + (0.25 * 50) = 14.5 cycles.

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A) The code will grab a block which has two longs, since the block size is 16B and a long is 8B. Since it progresses by column, it will always have the next item it needs in the cache, resulting in a miss at first and then a hit. The hit rate is 50\%.
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B) The code now progresses by row. It does not use the entire cache, and only uses some of the total sets. By the time it comes back to try to use an element it stored and needed, it is overwritten because there are only 2 blocks per set. Every time would result in a miss. The hit rate is 0\%.
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C) Compulsory Misses due to 2D matrix not being in cache when code starts.
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D) Conflict Misses due to only parts of the cache being used and not all of it.
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E) Increase the block size so that you can fit more memory locations in a block.
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F) Increase the set associativity so that there are more blocks present in a set.

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3A:
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i)
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ii)
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iii)
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3B)


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A) Each page is 2KB, the page offset will need 2$^x$ = 2048B. This will be 11 bits. The virtual memory address is 27 bits. The VPN is the remaining bits in the virtual address not including the offset. The VPN is 27-11 = 16 bits. Likewise the PPN is also the remaining bits in the physical address, so the PPN is 24-11 = 13 bits.
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B)
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D) Base and bounds registers are cheaper and faster.

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