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May 14th, 2019
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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    10:54:52 05/14/2019
  6. -- Design Name:
  7. -- Module Name:    uklad - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22.  
  23. -- Uncomment the following library declaration if using
  24. -- arithmetic functions with Signed or Unsigned values
  25. --use IEEE.NUMERIC_STD.ALL;
  26.  
  27. -- Uncomment the following library declaration if instantiating
  28. -- any Xilinx primitives in this code.
  29. --library UNISIM;
  30. --use UNISIM.VComponents.all;
  31.  
  32. entity uklad is
  33.     Port ( A : in  STD_LOGIC;
  34.            B : in  STD_LOGIC;
  35.            P : in  STD_LOGIC;
  36.            S : in  STD_LOGIC;
  37.            Y : out  STD_LOGIC;
  38.            Pw : out  STD_LOGIC);
  39. end uklad;
  40.  
  41. architecture Behavioral of uklad is
  42.  
  43. begin
  44. Y <= ((P and (not A) and (not B)) or ((not P) and (not A) and B) or (P and A and B) or ((not P) and A and (not B))) ;
  45. Pw <= ((P and (not S) and (not A) and (not B)) or ((not P) and (not S) and (not A) and B) or (S and B and A) or (P and B) or (P and S and A)) ;
  46.  
  47.  
  48. end Behavioral;
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