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  1. //commandbitdefinitions
  2. import cmd_bits::*;
  3.  
  4. module dev_fsm
  5. #(
  6.     // parameter declaration
  7.     parameter DW = 8    // data width
  8. )
  9. (
  10.     // inputs
  11.     input logic clk, rst, cs,
  12.     input logic [DW - 1:0] din,
  13.  
  14.     // outputs
  15.     output logic busy, drdy,
  16.     output logic [DW - 1:0] dout
  17. );
  18.    
  19.     // state register and next state value
  20.     enum logic [4:0] {ST_IDLE, ST_RCV_1, ST_RCV_2, ST_PROC, ST_TX} state, next_state;
  21.    
  22.     // data and status registers
  23.     logic [DW - 1:0] result;
  24.     logic [DW - 1:0] op_1;
  25.     logic [DW - 1:0] op_2;
  26.     logic [DW - 1:0] cmd;
  27.    
  28.     // state register
  29.     always_ff @ (posedge clk or negedge rst)
  30.     begin
  31.         if (~rst) state <= ST_IDLE;
  32.         else state <= next_state;
  33.     end
  34.  
  35.     //next state logic
  36.     always_comb
  37.     begin
  38.         next_state = state;
  39.         case (state)
  40.         ST_IDLE:
  41.             if (cs)
  42.             begin
  43.                 if (din[b_op_1]) next_state = ST_RCV_1;
  44.                 else if (din[b_op_2]) next_state = ST_RCV_2;
  45.                 else next_state = ST_PROC;
  46.             end
  47.         ST_RCV_1:
  48.             if (cmd[b_op_2]) next_state = ST_RCV_2;
  49.             else next_state = ST_PROC;
  50.         ST_RCV_2:
  51.             next_state = ST_PROC;
  52.         ST_PROC:
  53.             if (cmd[b_tx]) next_state = ST_TX;
  54.             else next_state = ST_IDLE;
  55.         ST_TX:
  56.             next_state = ST_IDLE;
  57.         default:
  58.             next_state = ST_IDLE;
  59.         endcase
  60.     end
  61.  
  62.     // data and status registers
  63.     always_ff @ (posedge clk or negedge rst)
  64.     begin
  65.         if (~rst)
  66.         begin
  67.             drdy <= 0;
  68.             busy <= 0;
  69.             result <= 0;
  70.             op_1 <= 0;
  71.             op_2 <= 0;
  72.             cmd <= 0;
  73.         end
  74.         else
  75.         begin
  76.             //since drdy is registered, set to 1 at the clock edge when state changes to ST_TX
  77.             drdy<=(next_state==ST_TX);
  78.             //we set busy to 0 at reset and when we enter idle
  79.             busy<=!(next_state==ST_IDLE);
  80.             //latching data in registers
  81.             case (state)
  82.             ST_IDLE:
  83.                 //store command in register when we leave idle
  84.                 if (cs) cmd<=din;
  85.             ST_RCV_1:
  86.                 //store operand 1
  87.                 op_1<=din;
  88.             ST_RCV_2:
  89.                 //store operand 2
  90.                 op_2<=din;
  91.             ST_PROC:
  92.                 //change result register according to opcode
  93.                 case (cmd[DW - 1:DW - 4])
  94.                     4'b1000: result <= op_1 + op_2;
  95.                     4'b0100: result <= op_1 - op_2;
  96.                     4'b0010: result <= result + op_1;
  97.                     4'b0001: result <= result - op_1;
  98.                 endcase
  99.             endcase
  100.         end
  101.     endb_tx
  102.  
  103.     assign dout = (state==ST_TX)?result:'bx;
  104.    
  105. endmodule
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