module combin(
  input [7:0] IN,
  output [15:0] OUT,
  input clk,
  input rst,
  input select
  );

  wire [15:0] OUTB;
  wire [15:0] OUTS;
  wire [3:0] stateb,states;
  srt CUT1(
     .IN(IN),
     .QUOTIENT(OUTS[15:8]),
     .REMAINDER(OUTS[7:0]),
     .clk(clk),
     .rst(rst)
     );
  boothR4 CUT2(
    .IN(IN),
    .OUT(OUTB),
    .clk(clk),
    .rst(rst)
    );

    assign OUT=select ?  OUTB : OUTS;
  endmodule