library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity risc_v is
    port(
        clk : std_logic;
        clk_mem : std_logic;
        rst : std_logic
    );
end entity;

architecture arch of risc_v is

    -- Sinais de memória (endereço e valores lidos)
    signal instr_address : std_logic_vector(7 downto 0) := x"00"; -- Endereço (de word) de instrução à ser lido
    signal data_address: std_logic_vector(7 downto 0) := x"00"; -- Endereço (de word) da memória à ser lido
    signal read_data: std_logic_vector(31 downto 0); -- Dado lido da memória de dados
    signal wb_data: std_logic_vector(31 downto 0); -- Dado que vai ser reescrito no registrador

    -- Sinais de PC
    signal pc_temp, pc_4, pc_offset : std_logic_vector(31 downto 0);
    signal pc : std_logic_vector(31 downto 0) := x"00000000";

    -- Sinais de controle
    signal zero, alusrc, mem2reg, memread, memwrite, branch, regwrite : std_logic;
    signal aluop : std_logic_vector(1 downto 0);

    -- Sinais da ULA
    signal A, B, Z, ro1, ro2 : std_logic_vector(31 downto 0);
    signal aluctr: std_logic_vector(3 downto 0);

    -- Sinais da instrução
    signal instr : std_logic_vector(31 downto 0);

    alias rs1    : std_logic_vector(4 downto 0) is instr(19 downto 15);
    alias rs2 : std_logic_vector(4 downto 0) is instr(24 downto 20);
    alias rd : std_logic_vector(4 downto 0) is instr(11 downto 7);
    alias opcode : std_logic_vector(6 downto 0) is instr(6 downto 0);
    alias funct7 : std_logic_vector(6 downto 0) is instr(31 downto 25);
    alias funct3 : std_logic_vector(2 downto 0) is instr(14 downto 12);

    -- Sinais do gerador de imediatos
    signal imm32: std_logic_vector(31 downto 0);

    constant c_four : std_logic_vector(31 downto 0) := x"00000004";

    -- Componentes (utilizar package!!!)
    component ula_rv is
        port (
            op      : in std_logic_vector(3 downto 0);
            A, B            : in std_logic_vector(31 downto 0);
            Z           : out std_logic_vector(31 downto 0);
            zero        : out std_logic);
    end component;

    component control IS
        PORT (
            opcode : IN std_logic_vector(6 DOWNTO 0);
            aluop: OUT std_logic_vector(1 DOWNTO 0);
            alusrc, mem2reg, regwrite, memread, memwrite, branch : OUT std_logic
        );
    END component;

    component alu_control IS
        PORT (
            funct7 : IN std_logic_vector(6 DOWNTO 0);
            funct3 : IN std_logic_vector(2 DOWNTO 0);
            aluop : IN std_logic_vector(1 DOWNTO 0);
            aluctr : OUT std_logic_vector(3 DOWNTO 0)
        );
    END component;

    component data_mem IS
        PORT
        (
            address     : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
            clock       : IN STD_LOGIC  := '1';
            data        : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
            wren        : IN STD_LOGIC ;
            q       : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
        );
    END component;

    component instr_mem IS
        PORT
        (
            address     : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
            clock       : IN STD_LOGIC  := '1';
            data        : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
            wren        : IN STD_LOGIC ;
            q       : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
        );
    END component;

    component XREGS is
        generic (WSIZE : natural := 32);
        port
        (
            clk, wren, rst : in std_logic;
            rs1, rs2, rd : in std_logic_vector(4 downto 0);
            data : in std_logic_vector(WSIZE-1 downto 0);
            ro1, ro2 : out std_logic_vector(WSIZE-1 downto 0)
        );
    end component;

    component genImm is
        port (
            instr : in std_logic_vector(31 downto 0);
            imm32 : out std_logic_vector(31 downto 0)
        );
    end component;

    component adder is
        generic (DATA_WIDTH : natural := 32);
        port
        (
            a      : in std_logic_vector  ((DATA_WIDTH-1) downto 0);
            b      : in std_logic_vector  ((DATA_WIDTH-1) downto 0);
            result : out std_logic_vector((DATA_WIDTH-1) downto 0)
        );
    end component;


begin
    instr_address <= pc(9 downto 2); -- O endereço de instrução é determinado pelo PC/4.
    data_address <= Z(9 downto 2); -- O endereço de dados é determinado pelo Z/4 (Z = saida da ULA).

    controller:
        control port map(
         opcode => opcode,
         memread => memread,
         mem2reg => mem2reg,
         memwrite => memwrite,
         alusrc => alusrc,
         regwrite => regwrite,
            aluop => aluop,
            branch => branch
        );

    registers :
        XREGS port map(
            clk => clk,
            wren => regwrite,
            rst => rst,
            rs1 => rs1,
            rs2 => rs2,
            rd => rd,
            data => wb_data,
            ro1 => ro1,
            ro2 => ro2
        );

    imm :
        genImm port map(
            instr => instr,
            imm32 => imm32
        );

    controller_alu :
        alu_control port map(
            funct3 => funct3,
            funct7 => funct7,
            aluop => aluop,
            aluctr => aluctr
        );

    data_memory :
        data_mem port map(
            address => data_address,
            clock => clk_mem,
            data => ro2,
            wren => memwrite,
            q => read_data
        );
    instr_memory :
        instr_mem port map(
            address => instr_address,
            clock => clk_mem,
            data => ro2,
            wren => '0',
            q => instr
        );

    adder_4 :
        adder port map(
            A => pc,
            B => c_four,
            result => pc_4
        );

    adder_imm :
        adder port map(
            A => pc,
            B => imm32,
            result => pc_offset
        );

    pc_temp <= pc_4 when ((branch and zero) = '0') else pc_offset;

    -- Multiplexação para decidir as entradas da ULA
    A <= ro1;
    B <= ro2 when (alusrc = '0') else imm32;

    alu :
    ula_rv port map(
        op => aluctr,
        A => A,
        B => B,
        Z => Z,
        zero => zero
        );


    -- Multiplexação para definir o valor de write-back
    wb_data <= Z when (mem2reg = '0') else read_data;

    process(clk)
    begin
        if(rising_edge(clk)) then
            pc <= pc_temp;
        end if;
    end process;
end architecture;