module ALU( A, B, SEL, FOUT );
input [3:0] A, B;
input [2:0] SEL;
output [4:0] FOUT;
reg [4:0] FOUT;

always @ ( SEL )
begin
    case( SEL )
    0               :   begin assign fout = a > b; end
    1               :   begin assign fout = b > a; end
    2               :   begin assign fout = {a[2:0], a[3]}; end
    3               :   begin assign fout = {a[0], a[3:1]}; end
    4               :   begin assign fout = a + b; end
    5               :   begin assign fout = a - b; end
    6               :   begin assign fout = b << 1; end
    7               :   begin assign fout = b >> 1; end
    default         :   fout = 5'b00000;
    endcase
end
endmodule