`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/21/2019 12:34:07 PM
// Design Name:
// Module Name: Main
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module Main(
    input clk,
    input wire[15:0] x1,x2,x3,x4,
    input wire[15:0] k1,k2,k3,k4,k5,k6,
    output reg[15:0] s0,s1,s2,s3
    );

    reg [15:0] p1,p2,p3,p4,p5,p6,p7,p8,p9,p10;
    Inmultire m1(x1,k1,p1);
    Inmultire m4(x4,k4,p4);
    Inmultire m5(p5,k5,p7);
    Inmultire m9(p8,k6,p9);
    always @(*)
    begin
        p2 = x2+k2;
        p3 = x3+k3;
        p5 = p1 ^ p3;
        p6 = p2 ^ p4;
        p8 = p6+p7;
        p10=p7+p9;

        s0= p1 ^ p9;
        s1= p3 ^ p9;
        s2= p2 ^ p10;
        s3= p4 ^ p10;
    end
endmodule