const int index = 16348;
const int way = 4;

struct cache
{
    int tag[4];
    int index[4];
    int LRU[4];
    int mesiState[4];
} L2;




void mesiOperation(struct L2 inL2 , bool transactionIN, bool cpuReadIN, bool cacheHitIN)
{
    bool MemoryRead = false;
    bool RFO = false;
    bool WriteBack = false;

    if(transactionIN == true)                                               //Cache Controller of Processor Accessing Memory
    {
        switch(inL2.mesiState)
        {
        case 0: // Invalidate
            if(cpuReadIN == true && cacheHitIN == true)
            {
                MemoryRead = true;
                RFO = false;
                WriteBack = false;
                inL2.mesiState = 2;
            }
            else if(cpuReadIN == true && cacheHitIN == false)
            {
                MemoryRead = true;
                RFO = false;
                WriteBack = false;
                mesiState = 1;
            }
            else if(cpuReadIN == false)
            {
                MemoryRead = false;
                RFO = true;
                WriteBack = false;
                mesiState = 3;
            }
            else
            {
                MemoryRead = false;
                RFO = false;
                WriteBack = false;
                mesiState = 0;
            }
        break;

        case 1: // Exclusive
            if(cpuReadIN == true)
            {
                MemoryRead = false;
                RFO = false;
                WriteBack = false;
                mesiState = 1;
            }
            else
            {
                MemoryRead = false;
                RFO = false;
                WriteBack = false;
                mesiState = 3;
            }
        break;

        case 2: // Shared
            if(cpuReadIN == true)
            {
                MemoryRead = false;
                RFO = false;
                WriteBack = false;
                mesiState = 2;
            }
            else
            {
                MemoryRead = false;
                RFO = true;
                WriteBack = false;
                mesiState = 3;
            }
        break;

        case 3: // Modified
            {
                MemoryRead = false;
                RFO = true;
                WriteBack = false;
                mesiState = 3;
            }
        break;
        }
    }