module Register (

    input wire c_CLOCKX,
    input wire c_CLOCKY,

    input wire f_SSRSet,

    output wire o_SSR,
    output wire [15:0] o_PC,
    output wire [15:0] o_PSP,
    output wire [15:0] o_RSP,
    output wire [15:0] o_OfR,
    output reg [15:0] o_REG,
);

reg SSR;
reg [15:0] registers [15:0];

assign o_SSR = SSR;
assign o_PC = registers[0];
assign o_PSP = registers[1];
assign o_RSP = registers[2];
assign o_OfR = registers[3];


always @ (negedge c_CLOCKX) begin
    SSR <= f_SSRSet;
end

endmodule