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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 08:22:46 09/13/2018
- -- Design Name:
- -- Module Name: tp06_ej01 - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- ---- Uncomment the following library declaration if instantiating
- ---- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity tp06_ej01 is
- Port ( C : in STD_LOGIC;
- B : in STD_LOGIC;
- A : in STD_LOGIC;
- Y : out STD_LOGIC);
- end tp06_ej01;
- architecture Behavioral of tp06_ej01 is
- begin
- Y<=(NOT C AND NOT B AND A)OR
- (NOT C AND B AND NOT A)OR
- (C AND NOT B AND NOT A)OR
- (C AND B AND A);
- end Behavioral;
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