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- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.numeric_std.ALL;
- USE work.ITCE211Project_library.ALL;
- ENTITY pe IS
- -- GENERIC (data_width : INTEGER := 8);
- PORT (
- eni, reset, clk : IN STD_LOGIC;
- numberin : INOUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
- numberout, number : INOUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
- eno : OUT STD_LOGIC
- );
- END pe;
- ARCHITECTURE behavior OF pe IS
- SIGNAL stored : STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0) := (OTHERS => '0');
- BEGIN
- PROCESS (clk)
- BEGIN
- IF rising_edge (clk) THEN
- IF eni = '1' THEN
- IF numberin > stored THEN
- eno <= '1';
- numberout <= stored;
- stored <= numberin;
- ELSE
- eno <= '1';
- numberout <= numberin;
- END IF;
- END IF;
- END IF;
- END PROCESS;
- END behavior;
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