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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. entity pulse is
  6. generic(N: integer range 0 to 32 := 8);
  7. port (
  8. clk    : in std_logic;
  9. reset  : in std_logic;                          
  10. trig   : in std_logic;                          
  11. pulse_len  : in UNSIGNED(N-1 downto 0);  
  12. wave   : out std_logic);
  13. end pulse;
  14.  
  15.  
  16. architecture rtl of pulse is
  17.  
  18. type FSM is (CZUWAJ, GENERUJ);
  19.  
  20. signal stan, stan_nast: FSM;
  21. signal stoper, zapisane_pl: UNSIGNED(N-1 downto 0);
  22. signal zeruj: std_logic;
  23.  
  24. begin
  25.  
  26. STATE_REG_PROC:
  27. process (reset, clk)
  28. begin
  29.   if(reset='0') then
  30.     stan <= CZUWAJ;
  31.   elsif(rising_edge(clk)) then
  32.     stan <= stan_nast;
  33.    
  34.   end if;
  35. end process;
  36.  
  37.  
  38. NEXT_STATE_PROC:
  39. process (clk)
  40. begin
  41.     case stan is
  42.      when CZUWAJ =>
  43.        if(trig='1' and not (zapisane_pl =0)) then
  44.          stan_nast<=GENERUJ;
  45.          --zeruj<='0';
  46.          else
  47.            stan_nast<=CZUWAJ;
  48.            zeruj <= '0';
  49.        end if;
  50.        
  51.        when GENERUJ =>
  52.          if(stoper<zapisane_pl-1) then
  53.            stan_nast <= CZUWAJ;
  54.            zeruj <= '1';
  55.           elsif(trig='1') then
  56.              stan_nast <= CZUWAJ;
  57.              zeruj <='1';
  58.             else
  59.                stan_nast<=GENERUJ;
  60.                
  61.           end if;
  62.          
  63.          
  64.    
  65.      end case;
  66. end process;
  67.  
  68.  
  69. WAVE_PROC:
  70. process (stan)
  71. begin
  72.     case stan is
  73.     when CZUWAJ =>
  74.       wave <= '0';
  75.     when GENERUJ =>
  76.       wave <= '1';
  77.  
  78.     end case;
  79. end process;
  80.  
  81. TIMER_PROC:
  82. process (clk,trig)
  83. begin
  84. if (reset = '0' or stan =CZUWAJ or zeruj = '1') then
  85.   stoper <= (others => '0');
  86. elsif (rising_edge(clk)) then
  87.   stoper <= stoper+1;
  88.   end if;
  89.  
  90. end process;
  91.  
  92.  
  93. SAVE_PULSE_LEN_PROC:
  94. process (clk, reset)
  95. begin
  96.   if(rising_edge(clk)) then
  97.     if (pulse_len=0 )then
  98.       zapisane_pl <= to_unsigned(1,N);
  99.   else
  100.     zapisane_pl <=pulse_len;
  101.   end if;
  102.   end if;
  103. end process;
  104.  
  105. end rtl;
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