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- =================================================================
- //OG.v
- module OG(input q1, q2, q3, output o);
- assign o = (q3);
- endmodule
- =================================================================
- //NSG.v
- module NSG(input x, q1, q2, q3, output d1, d2, d3);
- assign d3 = (x & q2 & q1);
- assign d2 = (x & q2 & q1) | ((~x) & q2 & (~q1));
- assign d1 = (q2 & (~q1)) | (x & (~q1));
- endmodule
- =================================================================
- //FF.v
- module FF(input d, clk, r, output reg q);
- always @(posedge clk, negedge r)
- begin
- if(clk)
- q <= d;
- else if(!r)
- q <= r;
- end
- endmodule
- =================================================================
- //FSM.v
- `include "OG.v"
- `include "NSG.v"
- `include "FF.v"
- module FSM(input x, clk, r, output o);
- wire q1, q2, q3, d1, d2, d3, o;
- NSG next(x, q1, q2, q3, d1, d2, d3);
- FF ff1(d1, clik, r, q1);
- FF ff2(d2, clik, r, q2);
- FF ff3(d3, clik, r, q3);
- OG out(q1, q2, q3, o);
- endmodule
- =================================================================
- //main.v
- `include "FSM.v"
- module main;
- reg x, clk, r;
- wire o;
- initial
- begin
- clk= 1;
- r = 0;
- x = 0;
- #1;
- r = 1;
- end
- initial
- begin
- $monitor(" x=%x t=%3d o=%x ", x, $time, o);
- end
- initial
- repeat( 16 )
- begin
- #1 clk = ~clk;
- end
- initial
- //1011011010110100
- begin
- #2
- #1 x = 1;
- #1 x = 0;
- #1 x = 1;
- #1 x = 1;
- #1 x = 0;
- #1 x = 1;
- #1 x = 1;
- #1 x = 0;
- #1 x = 1;
- #1 x = 0;
- #1 x = 1;
- #1 x = 1;
- #1 x = 0;
- #1 x = 1;
- #1 x = 0;
- #1 x = 0;
- end
- endmodule
- =================================================================
- Output
- x=0 t=1 o=0
- x=0 t=2 o=0
- x=1 t=4 o=0
- x=0 t=6 o=0
- x=1 t=8 o=0
- x=1 t=10 o=0
- x=0 t=12 o=0
- x=1 t=14 o=1
- x=1 t=16 o=0
- x=0 t=18 o=0
- x=1 t=20 o=1
- x=0 t=22 o=0
- x=1 t=24 o=0
- x=1 t=26 o=0
- x=0 t=28 o=1
- x=1 t=30 o=0
- x=0 t=32 o=0
- x=0 t=34 o=0
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