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  1. module check_parity(clk, serial_in, received_data, data_is_valid, is_parity_stage, rx_error); // even parity checker
  2.  
  3. input clk, serial_in, data_is_valid, is_parity_stage;
  4. input [7:0] received_data;
  5. output reg rx_error = 0;
  6.  
  7. reg parity_value; // this is being computed from the received 8-bit data
  8. reg parity_bit;  // this bit is received directly through UART
  9.  
  10. always @(posedge clk)
  11. begin
  12.     parity_value <= ^(received_data);
  13. end
  14.  
  15. always @(posedge clk)
  16. begin
  17.     if (is_parity_stage)
  18.     parity_bit <= serial_in;
  19. end
  20.  
  21. always @(posedge clk)
  22. begin
  23.     if ((data_is_valid) && (parity_bit != parity_value))
  24.     rx_error <= 1;
  25. end
  26.  
  27. endmodule
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