`define DATASET_BITS 11
module GeneticAlg#(
        parameter NCOUNT = 128,//number of all neurons
        parameter DSAWIDTH = 10,//bit size of dataset address bus
        parameter ROW_SIZE = 31,//size of data row in network
        parameter NET_DELAY = 64 //net delay to stabilize result
    )(
        input wire clk,

        //address bus for all neurons
        output wire writeEnable,
        output wire[clog2(NCOUNT*32-1)-1:0] memAddr,
        output wire[16:0] memData,

        //network input and output
        output wire[`DATASET_BITS*ROW_SIZE-1:0] netParams,
        input wire[`DATASET_BITS*ROW_SIZE-1:0] netResult,

        //dataset memory buses
        input wire[15:0] rowCount,//number of data rows in memory, memory size = rowCount*ROW_SIZE
        output wire[DSAWIDTH-1:0] datasetAddr,//addres of data
        input wire[`DATASET_BITS-1:0] datasetData//read is delayed by 1 cycle
    );