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- library ieee;
- use ieee.std_logic_1164.all;
- entity circuit_1 is
- port (
- pin_name : in STD_LOGIC;
- pin_name1 : in STD_LOGIC;
- pin_name2 : in STD_LOGIC;
- pin_name6 : out STD_LOGIC);
- end circuit_1;
- architecture Behavioral of circuit_1 is
- begin
- pin_name6 <= ( (pin_name and pin_name1) or ((not pin_name) and (not pin_name1) and pin_name2));
- end Behavioral;
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