circuitosdigitais_exe4

library ieee;
use ieee.std_logic_1164.all;

entity Topo is port (
	SW: in std_logic_vector(9 downto 0);
	KEY: in std_logic_vector(3 downto 0);
	LEDR: out std_logic_vector(7 downto 0);
	HEX0: out std_logic_vector(6 downto 0);
	HEX1: out std_logic_vector(6 downto 0);
	CLOCK_50: in std_logic
);
end Topo;

architecture topo_beh of Topo is
signal BTN: std_logic_vector(3 downto 0);
signal LED: std_logic_vector(7 downto 0);

component ButtonSync is
	port
	(
		KEY0, KEY1, KEY2, KEY3, CLK: in std_logic;
		BTN0, BTN1, BTN2, BTN3: out std_logic
	);
end component;

component decod is
port (H: in std_logic_vector(3 downto 0);
C: out std_logic_vector(6 downto 0)
);
end component;

component Multimodo is port (
	SW: in std_logic_vector(7 downto 0);
	muxInput: in std_logic_vector(1 downto 0);
	BTN0: in std_logic; --Reset
	BTN1: in std_logic; --LOad
	clock: in std_logic;
	LED: out std_logic_vector(7 downto 0)
	);
end component;

Begin
	C0: ButtonSync port map (KEY(0),KEY(1),KEY(2), KEY(3), CLOCK_50, BTN(0), BTN(1), BTN(2), BTN(3));
	M0: Multimodo port map (SW(7 downto 0), SW(9 downto 8), BTN(0) , BTN(1), CLOCK_50, LED);
	DC1: decod port map (LED(3 downto 0),HEX0);
   DC2: decod port map (LED(7 downto 4),HEX1);
	LEDR <= LED;
end topo_beh;

---------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity Multimodo is port (
	SW: in std_logic_vector(7 downto 0);
	muxInput: in std_logic_vector(1 downto 0);
	BTN0: in std_logic; --Reset
	BTN1: in std_logic; --LOad
	clock: in std_logic;
	LED: out std_logic_vector(7 downto 0)
	);
end Multimodo;

architecture arqdtp of Multimodo is
signal tot: std_logic_vector(7 downto 0);
signal muxValue: std_logic_vector(7 downto 0);
signal dir: std_logic_vector(7 downto 0);
signal esq: std_logic_vector(7 downto 0);
begin

dir <= '0'&tot(7 downto 1);
esq <= tot(6 downto 0)&'0';

muxValue <= tot + SW when muxInput = "00" else
				SW when muxInput = "01" else
				dir when muxInput = "10" else
				esq when muxInput = "11";


-- Registrador e Somador:
process(clock,BTN0,BTN1)
begin
	if (BTN0 = '0') then
		tot <= "00000000";
	elsif (clock'event AND clock = '1') then
		if (BTN1 = '0') then
			tot <= muxValue;
		end if;
	end if;
end process;
LED <= tot;
end arqdtp;

------------------------------------------------------------
-- Button Press Synchronizer para keys que são ativas baixas (ou seja, quando pressionadas vao para nivel baixo)

library ieee;
use ieee.std_logic_1164.all;

entity ButtonSync is
	port
	(
		KEY0, KEY1, KEY2, KEY3, CLK: in std_logic;
		BTN0, BTN1, BTN2, BTN3: out std_logic
	);
end ButtonSync;


architecture ButtonSyncImpl of ButtonSync is
type STATES is (EsperaApertar, SaidaAtiva, EsperaSoltar);
signal btn0state, btn1state, btn2state, btn3state : STATES := EsperaApertar;
signal btn0next, btn1next, btn2next, btn3next : STATES := EsperaApertar;
begin

	process (clk)
	begin
		if clk'event and clk = '1' then -- Resposta na transicao positiva do clock
			btn0state <= btn0next;
			btn1state <= btn1next;
			btn2state <= btn2next;
			btn3state <= btn3next;
		end if;
	end process;

	process (key0,btn0state)
	begin
		case btn0state is
			when EsperaApertar =>
				if key0 = '0' then btn0next <= SaidaAtiva; else btn0next <= EsperaApertar; end if;
				btn0 <= '1';
			when SaidaAtiva =>
				if key0 = '0' then btn0next <= EsperaSoltar; else btn0next <= EsperaApertar; end if;
				btn0 <= '0';
			when EsperaSoltar =>
				if key0 = '0' then btn0next <= EsperaSoltar;	else btn0next <= EsperaApertar; end if;
				btn0 <= '1';
		end case;
	end process;

	process (key1,btn1state)
	begin
		case btn1state is
			when EsperaApertar =>
				if key1 = '0' then btn1next <= SaidaAtiva; else btn1next <= EsperaApertar; end if;
				btn1 <= '1';
			when SaidaAtiva =>
				if key1 = '0' then btn1next <= EsperaSoltar; else btn1next <= EsperaApertar; end if;
				btn1 <= '0';
			when EsperaSoltar =>
				if key1 = '0' then btn1next <= EsperaSoltar;	else btn1next <= EsperaApertar; end if;
				btn1 <= '1';
		end case;
	end process;

	process (key2,btn2state)
	begin
		case btn2state is
			when EsperaApertar =>
				if key2 = '0' then btn2next <= SaidaAtiva; else btn2next <= EsperaApertar; end if;
				btn2 <= '1';
			when SaidaAtiva =>
				if key2 = '0' then btn2next <= EsperaSoltar; else btn2next <= EsperaApertar; end if;
				btn2 <= '0';
			when EsperaSoltar =>
				if key2 = '0' then btn2next <= EsperaSoltar;	else btn2next <= EsperaApertar; end if;
				btn2 <= '1';
		end case;
	end process;

	process (key3,btn3state)
	begin
		case btn3state is
			when EsperaApertar =>
				if key3 = '0' then btn3next <= SaidaAtiva; else btn3next <= EsperaApertar; end if;
				btn3 <= '1';
			when SaidaAtiva =>
				if key3 = '0' then btn3next <= EsperaSoltar; else btn3next <= EsperaApertar; end if;
				btn3 <= '0';
			when EsperaSoltar =>
				if key3 = '0' then btn3next <= EsperaSoltar;	else btn3next <= EsperaApertar; end if;
				btn3 <= '1';
		end case;
	end process;

end ButtonSyncImpl;
------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;

entity decod is
port (H: in std_logic_vector(3 downto 0);
C: out std_logic_vector(6 downto 0)
);
end entity;

architecture decoder of decod is
begin
C <=  "1000000" when H = "0000" else
		"1111001" when H = "0001" else
		"0100100" when H = "0010" else
		"0110000" when H = "0011" else
		"0011001" when H = "0100" else
		"0010010" when H = "0101" else
		"0000010" when H = "0110" else
		"1111000" when H = "0111" else
		"0000000" when H = "1000" else
		"0011000" when H = "1001" else
		"0001000" when H = "1010" else
		"0000011" when H = "1011" else
		"1000110" when H = "1100" else
		"0100001" when H = "1101" else
		"0000110" when H = "1110" else
		"0001110";

end architecture;