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Oct 15th, 2020
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  1. LIBRARY IEEE;
  2. USE IEEE.std_logic_1164.ALL;
  3. USE IEEE.numeric_std.ALL;
  4.  
  5. ENTITY rs232_tx_test IS
  6.   GENERIC(clk_period: TIME := 41666666.7 fs;
  7.           baud_period: TIME := 8680.55556 ns);
  8. END rs232_tx_test;
  9.  
  10. ARCHITECTURE working OF rs232_tx_test IS
  11.   SIGNAL clk: STD_LOGIC := '0';
  12.   SIGNAL tx, rst, fifo_empty, fifo_RdEn, fifo_RdClock: STD_LOGIC;
  13.   SIGNAL fifo_data: STD_LOGIC_VECTOR(7 DOWNTO 0);
  14. BEGIN
  15.   clk <= NOT clk AFTER clk_period/2;
  16.   rst <= '1', '0' AFTER 100 ns;
  17.   PROCESS
  18.   BEGIN
  19.     fifo_empty <= '1';
  20.     WAIT FOR baud_period;
  21.     fifo_empty <= '0';
  22.     WAIT FOR baud_period*16;
  23.   END PROCESS;
  24.  
  25.   fifo_data <= ('1','1','0','0','1','0','1','1') WHEN fifo_RdEn='1' ELSE (others=>'0');
  26.   dut: ENTITY work.rs232_tx
  27.     PORT MAP(clk,tx,rst,fifo_empty,fifo_RdEn,fifo_RdClock,fifo_data);
  28. END working;
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