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- -- VHDL Entity Lab5VHDL_lib.Lab5VHDL.symbol
- --
- -- Created:
- -- by - stud.stud (mmf417-8)
- -- at - 17:50:11 05/15/19
- --
- -- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
- --
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_arith.all;
- ENTITY Lab5VHDL IS
- PORT(
- clk : IN std_logic;
- dataIn : IN std_logic_vector (2 DOWNTO 0);
- rst : IN std_logic;
- dataOut : OUT std_logic_vector (2 DOWNTO 0)
- );
- -- Declarations
- END Lab5VHDL ;
- --
- -- VHDL Architecture Lab5VHDL_lib.Lab5VHDL.fsm
- --
- -- Created:
- -- by - stud.stud (mmf417-8)
- -- at - 17:50:11 05/15/19
- --
- -- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
- --
- LIBRARY ieee;
- USE ieee.std_logic_1164.all;
- USE ieee.std_logic_arith.all;
- ARCHITECTURE fsm OF Lab5VHDL IS
- TYPE STATE_TYPE IS (
- s11,
- s22,
- s3
- );
- -- Declare current and next state signals
- SIGNAL current_state : STATE_TYPE;
- SIGNAL next_state : STATE_TYPE;
- BEGIN
- -----------------------------------------------------------------
- clocked_proc : PROCESS (
- clk,
- rst
- )
- -----------------------------------------------------------------
- BEGIN
- IF (rst = '0') THEN
- current_state <= s11;
- ELSIF (clk'EVENT AND clk = '1') THEN
- current_state <= next_state;
- END IF;
- END PROCESS clocked_proc;
- -----------------------------------------------------------------
- nextstate_proc : PROCESS (
- current_state,
- dataIn
- )
- -----------------------------------------------------------------
- BEGIN
- CASE current_state IS
- WHEN s11 =>
- IF (dataIn = "001") THEN
- next_state <= s11;
- ELSIF (dataIn = "010") THEN
- next_state <= s3;
- ELSIF (dataIn = "100") THEN
- next_state <= s22;
- ELSE
- next_state <= s11;
- END IF;
- WHEN s22 =>
- IF (dataIn = "001" or dataIn = "010") THEN
- next_state <= s11;
- ELSIF (dataIn = "100") THEN
- next_state <= s22;
- ELSE
- next_state <= s22;
- END IF;
- WHEN s3 =>
- IF (dataIn = "001" or dataIn = "010") THEN
- next_state <= s22;
- ELSIF (dataIn = "100") THEN
- next_state <= s3;
- ELSE
- next_state <= s3;
- END IF;
- WHEN OTHERS =>
- next_state <= s11;
- END CASE;
- END PROCESS nextstate_proc;
- -----------------------------------------------------------------
- output_proc : PROCESS (
- current_state
- )
- -----------------------------------------------------------------
- BEGIN
- -- Combined Actions
- CASE current_state IS
- WHEN s11 =>
- dataOut <= "010";
- WHEN s22 =>
- dataOut <= "100";
- WHEN s3 =>
- dataOut <= "001";
- WHEN OTHERS =>
- NULL;
- END CASE;
- END PROCESS output_proc;
- END fsm;
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