shchuko

pci_lpc.c

Sep 14th, 2020
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  1. /*-
  2.  * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
  3.  * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
  4.  * Copyright (c) 2015 xhyve developers
  5.  * All rights reserved.
  6.  *
  7.  * Redistribution and use in source and binary forms, with or without
  8.  * modification, are permitted provided that the following conditions
  9.  * are met:
  10.  * 1. Redistributions of source code must retain the above copyright
  11.  *    notice, this list of conditions and the following disclaimer.
  12.  * 2. Redistributions in binary form must reproduce the above copyright
  13.  *    notice, this list of conditions and the following disclaimer in the
  14.  *    documentation and/or other materials provided with the distribution.
  15.  *
  16.  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
  17.  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18.  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19.  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
  20.  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21.  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22.  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23.  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24.  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25.  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26.  * SUCH DAMAGE.
  27.  *
  28.  * $FreeBSD$
  29.  */
  30.  
  31. #include <stdio.h>
  32. #include <stdlib.h>
  33. #include <string.h>
  34. #include <xhyve/vmm/vmm_api.h>
  35. #include <xhyve/acpi.h>
  36. #include <xhyve/bootrom.h>
  37. #include <xhyve/inout.h>
  38. #include <xhyve/dbgport.h>
  39. #include <xhyve/pci_emul.h>
  40. #include <xhyve/pci_irq.h>
  41. #include <xhyve/pci_lpc.h>
  42. #include <xhyve/uart_emul.h>
  43.  
  44. #define IO_ICU1     0x20
  45. #define IO_ICU2     0xA0
  46.  
  47. SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt);
  48. SET_DECLARE(lpc_sysres_set, struct lpc_sysres);
  49.  
  50. #define ELCR_PORT   0x4d0
  51. SYSRES_IO(ELCR_PORT, 2);
  52.  
  53. #define IO_TIMER1_PORT  0x40
  54.  
  55. #define NMISC_PORT  0x61
  56. SYSRES_IO(NMISC_PORT, 1);
  57.  
  58. static struct pci_devinst *lpc_bridge;
  59.  
  60. static const char *romfile;
  61.  
  62. #define LPC_UART_NUM    2
  63.  
  64. #pragma clang diagnostic push
  65. #pragma clang diagnostic ignored "-Wpadded"
  66. static struct lpc_uart_softc {
  67.     struct uart_softc *uart_softc;
  68.     const char *opts;
  69.     const char *name;
  70.     int iobase;
  71.     int irq;
  72.     int enabled;
  73. } lpc_uart_softc[LPC_UART_NUM];
  74. #pragma clang diagnostic pop
  75.  
  76. static const char *lpc_uart_names[LPC_UART_NUM] = { "COM1", "COM2" };
  77.  
  78. /*
  79.  * LPC device configuration is in the following form:
  80.  * <lpc_device_name>[,<options>]
  81.  * For e.g. "com1,stdio" or "bootrom,/var/romfile"
  82.  */
  83. int
  84. lpc_device_parse(const char *opts)
  85. {
  86.     int unit, error;
  87.     char *str, *cpy, *lpcdev;
  88.  
  89.     error = -1;
  90.     str = cpy = strdup(opts);
  91.     lpcdev = strsep(&str, ",");
  92.     if (lpcdev != NULL) {
  93.         if (strcasecmp(lpcdev, "bootrom") == 0) {
  94.             romfile = str;
  95.             error = 0;
  96.             goto done;
  97.         }
  98.         for (unit = 0; unit < LPC_UART_NUM; unit++) {
  99.             if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) {
  100.                 lpc_uart_softc[unit].opts = str;
  101.                 lpc_uart_softc[unit].name = lpc_uart_names[unit];
  102.                 error = 0;
  103.                 goto done;
  104.             }
  105.         }
  106.     }
  107.  
  108. done:
  109.     if (error)
  110.         free(cpy);
  111.  
  112.     return (error);
  113. }
  114.  
  115. const char *
  116. lpc_bootrom(void)
  117. {
  118.     return romfile;
  119. }
  120.  
  121.  
  122. static void
  123. lpc_uart_intr_assert(void *arg)
  124. {
  125.     struct lpc_uart_softc *sc = arg;
  126.  
  127.     assert(sc->irq >= 0);
  128.  
  129.     xh_vm_isa_pulse_irq(sc->irq, sc->irq);
  130. }
  131.  
  132. static void
  133. lpc_uart_intr_deassert(UNUSED void *arg)
  134. {
  135.     /*
  136.      * The COM devices on the LPC bus generate edge triggered interrupts,
  137.      * so nothing more to do here.
  138.      */
  139. }
  140.  
  141. static int
  142. lpc_uart_io_handler(UNUSED int vcpu, int in, int port, int bytes, uint32_t *eax,
  143.     void *arg)
  144. {
  145.     int offset;
  146.     struct lpc_uart_softc *sc = arg;
  147.  
  148.     offset = port - sc->iobase;
  149.  
  150.     switch (bytes) {
  151.     case 1:
  152.         if (in)
  153.             *eax = uart_read(sc->uart_softc, offset);
  154.         else
  155.             uart_write(sc->uart_softc, offset, ((uint8_t) *eax));
  156.         break;
  157.     case 2:
  158.         if (in) {
  159.             *eax = (uint32_t) uart_read(sc->uart_softc, offset);
  160.             *eax |= (uint32_t) (uart_read(sc->uart_softc, offset + 1) << 8);
  161.         } else {
  162.             uart_write(sc->uart_softc, offset, ((uint8_t) *eax));
  163.             uart_write(sc->uart_softc, offset + 1, ((uint8_t) (*eax >> 8)));
  164.         }
  165.         break;
  166.     case 4:
  167.         if (in) {
  168.             *eax = (uint32_t) uart_read(sc->uart_softc, offset);
  169.             *eax |= (uint32_t) (uart_read(sc->uart_softc, offset + 1) << 8);
  170.             *eax |= (uint32_t) (uart_read(sc->uart_softc, offset + 2) << 16);
  171.             *eax |= (uint32_t) (uart_read(sc->uart_softc, offset + 3) << 24);
  172.         } else {
  173.             uart_write(sc->uart_softc, offset, ((uint8_t) (*eax)));
  174.             uart_write(sc->uart_softc, offset + 1, ((uint8_t) (*eax >> 8)));
  175.             uart_write(sc->uart_softc, offset + 2, ((uint8_t) (*eax >> 16)));
  176.             uart_write(sc->uart_softc, offset + 3, ((uint8_t) (*eax >> 24)));
  177.         }
  178.         break
  179.     default:
  180.         return (-1);
  181.     }
  182.  
  183.     return (0);
  184. }
  185.  
  186. static int
  187. lpc_init(void)
  188. {
  189.     struct lpc_uart_softc *sc;
  190.     struct inout_port iop;
  191.     int unit, error;
  192.  
  193.     if (romfile != NULL) {
  194.         error = bootrom_init(romfile);
  195.         if (error)
  196.             return error;
  197.     }
  198.  
  199.     /* COM1 and COM2 */
  200.     for (unit = 0; unit < LPC_UART_NUM; unit++) {
  201.         sc = &lpc_uart_softc[unit];
  202.  
  203.         if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) {
  204.             fprintf(stderr, "Unable to allocate resources for "
  205.                 "LPC device %s\n", sc->name);
  206.             return (-1);
  207.         }
  208.         pci_irq_reserve(sc->irq);
  209.  
  210.         sc->uart_softc = uart_init(lpc_uart_intr_assert,
  211.                     lpc_uart_intr_deassert, sc);
  212.  
  213.         if (uart_set_backend(sc->uart_softc, sc->opts, sc->name) != 0) {
  214.             fprintf(stderr, "Unable to initialize backend '%s' "
  215.                 "for LPC device %s\n", sc->opts, sc->name);
  216.             return (-1);
  217.         }
  218.  
  219.         bzero(&iop, sizeof(struct inout_port));
  220.         iop.name = sc->name;
  221.         iop.port = sc->iobase;
  222.         iop.size = UART_IO_BAR_SIZE;
  223.         iop.flags = IOPORT_F_INOUT;
  224.         iop.handler = lpc_uart_io_handler;
  225.         iop.arg = sc;
  226.  
  227.         error = register_inout(&iop);
  228.         assert(error == 0);
  229.         sc->enabled = 1;
  230.     }
  231.  
  232.     return (0);
  233. }
  234.  
  235. static void
  236. pci_lpc_write_dsdt(struct pci_devinst *pi)
  237. {
  238.     struct lpc_dsdt **ldpp, *ldp;
  239.  
  240.     dsdt_line("");
  241.     dsdt_line("Device (ISA)");
  242.     dsdt_line("{");
  243.     dsdt_line("  Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func);
  244.     dsdt_line("  OperationRegion (LPCR, PCI_Config, 0x00, 0x100)");
  245.     dsdt_line("  Field (LPCR, AnyAcc, NoLock, Preserve)");
  246.     dsdt_line("  {");
  247.     dsdt_line("    Offset (0x60),");
  248.     dsdt_line("    PIRA,   8,");
  249.     dsdt_line("    PIRB,   8,");
  250.     dsdt_line("    PIRC,   8,");
  251.     dsdt_line("    PIRD,   8,");
  252.     dsdt_line("    Offset (0x68),");
  253.     dsdt_line("    PIRE,   8,");
  254.     dsdt_line("    PIRF,   8,");
  255.     dsdt_line("    PIRG,   8,");
  256.     dsdt_line("    PIRH,   8");
  257.     dsdt_line("  }");
  258.     dsdt_line("");
  259.  
  260.     dsdt_indent(1);
  261.     SET_FOREACH(ldpp, lpc_dsdt_set) {
  262.         ldp = *ldpp;
  263.         ldp->handler();
  264.     }
  265.  
  266.     dsdt_line("");
  267.     dsdt_line("Device (PIC)");
  268.     dsdt_line("{");
  269.     dsdt_line("  Name (_HID, EisaId (\"PNP0000\"))");
  270.     dsdt_line("  Name (_CRS, ResourceTemplate ()");
  271.     dsdt_line("  {");
  272.     dsdt_indent(2);
  273.     dsdt_fixed_ioport(IO_ICU1, 2);
  274.     dsdt_fixed_ioport(IO_ICU2, 2);
  275.     dsdt_fixed_irq(2);
  276.     dsdt_unindent(2);
  277.     dsdt_line("  })");
  278.     dsdt_line("}");
  279.  
  280.     dsdt_line("");
  281.     dsdt_line("Device (TIMR)");
  282.     dsdt_line("{");
  283.     dsdt_line("  Name (_HID, EisaId (\"PNP0100\"))");
  284.     dsdt_line("  Name (_CRS, ResourceTemplate ()");
  285.     dsdt_line("  {");
  286.     dsdt_indent(2);
  287.     dsdt_fixed_ioport(IO_TIMER1_PORT, 4);
  288.     dsdt_fixed_irq(0);
  289.     dsdt_unindent(2);
  290.     dsdt_line("  })");
  291.     dsdt_line("}");
  292.     dsdt_unindent(1);
  293.  
  294.     dsdt_line("}");
  295. }
  296.  
  297. static void
  298. pci_lpc_sysres_dsdt(void)
  299. {
  300.     struct lpc_sysres **lspp, *lsp;
  301.  
  302.     dsdt_line("");
  303.     dsdt_line("Device (SIO)");
  304.     dsdt_line("{");
  305.     dsdt_line("  Name (_HID, EisaId (\"PNP0C02\"))");
  306.     dsdt_line("  Name (_CRS, ResourceTemplate ()");
  307.     dsdt_line("  {");
  308.  
  309.     dsdt_indent(2);
  310.     SET_FOREACH(lspp, lpc_sysres_set) {
  311.         lsp = *lspp;
  312.         switch (lsp->type) {
  313.         case LPC_SYSRES_IO:
  314.             dsdt_fixed_ioport(((uint16_t) lsp->base), ((uint16_t) lsp->length));
  315.             break;
  316.         case LPC_SYSRES_MEM:
  317.             dsdt_fixed_mem32(lsp->base, lsp->length);
  318.             break;
  319.         }
  320.     }
  321.     dsdt_unindent(2);
  322.  
  323.     dsdt_line("  })");
  324.     dsdt_line("}");
  325. }
  326. LPC_DSDT(pci_lpc_sysres_dsdt);
  327.  
  328. static void
  329. pci_lpc_uart_dsdt(void)
  330. {
  331.     struct lpc_uart_softc *sc;
  332.     int unit;
  333.  
  334.     for (unit = 0; unit < LPC_UART_NUM; unit++) {
  335.         sc = &lpc_uart_softc[unit];
  336.         if (!sc->enabled)
  337.             continue;
  338.         dsdt_line("");
  339.         dsdt_line("Device (%s)", lpc_uart_names[unit]);
  340.         dsdt_line("{");
  341.         dsdt_line("  Name (_HID, EisaId (\"PNP0501\"))");
  342.         dsdt_line("  Name (_UID, %d)", unit + 1);
  343.         dsdt_line("  Name (_CRS, ResourceTemplate ()");
  344.         dsdt_line("  {");
  345.         dsdt_indent(2);
  346.         dsdt_fixed_ioport(((uint16_t) sc->iobase), UART_IO_BAR_SIZE);
  347.         dsdt_fixed_irq(((uint8_t) sc->irq));
  348.         dsdt_unindent(2);
  349.         dsdt_line("  })");
  350.         dsdt_line("}");
  351.     }
  352. }
  353. LPC_DSDT(pci_lpc_uart_dsdt);
  354.  
  355. static int
  356. pci_lpc_cfgwrite(UNUSED int vcpu, struct pci_devinst *pi, int coff, int bytes,
  357.     uint32_t val)
  358. {
  359.     int pirq_pin;
  360.  
  361.     if (bytes == 1) {
  362.         pirq_pin = 0;
  363.         if (coff >= 0x60 && coff <= 0x63)
  364.             pirq_pin = coff - 0x60 + 1;
  365.         if (coff >= 0x68 && coff <= 0x6b)
  366.             pirq_pin = coff - 0x68 + 5;
  367.         if (pirq_pin != 0) {
  368.             pirq_write(pirq_pin, ((uint8_t) val));
  369.             pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin));
  370.             return (0);
  371.         }
  372.     }
  373.     return (-1);
  374. }
  375.  
  376. static void
  377. pci_lpc_write(UNUSED int vcpu, UNUSED struct pci_devinst *pi, UNUSED int baridx,
  378.     UNUSED uint64_t offset, UNUSED int size, UNUSED uint64_t value)
  379. {
  380. }
  381.  
  382. static uint64_t
  383. pci_lpc_read(UNUSED int vcpu, UNUSED struct pci_devinst *pi, UNUSED int baridx,
  384.     UNUSED uint64_t offset, UNUSED int size)
  385. {
  386.     return (0);
  387. }
  388.  
  389. #define LPC_DEV     0x7000
  390. #define LPC_VENDOR  0x8086
  391.  
  392. static int
  393. pci_lpc_init(struct pci_devinst *pi, UNUSED char *opts)
  394. {
  395.  
  396.     /*
  397.      * Do not allow more than one LPC bridge to be configured.
  398.      */
  399.     if (lpc_bridge != NULL) {
  400.         fprintf(stderr, "Only one LPC bridge is allowed.\n");
  401.         return (-1);
  402.     }
  403.  
  404.     /*
  405.      * Enforce that the LPC can only be configured on bus 0. This
  406.      * simplifies the ACPI DSDT because it can provide a decode for
  407.      * all legacy i/o ports behind bus 0.
  408.      */
  409.     if (pi->pi_bus != 0) {
  410.         fprintf(stderr, "LPC bridge can be present only on bus 0.\n");
  411.         return (-1);
  412.     }
  413.  
  414.     if (lpc_init() != 0)
  415.         return (-1);
  416.  
  417.     /* initialize config space */
  418.     pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV);
  419.     pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR);
  420.     pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE);
  421.     pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA);
  422.  
  423.     lpc_bridge = pi;
  424.  
  425.     return (0);
  426. }
  427.  
  428. char *
  429. lpc_pirq_name(int pin)
  430. {
  431.     char *name;
  432.  
  433.     if (lpc_bridge == NULL)
  434.         return (NULL);
  435.     asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1);
  436.     return (name);
  437. }
  438.  
  439. void
  440. lpc_pirq_routed(void)
  441. {
  442.     int pin;
  443.  
  444.     if (lpc_bridge == NULL)
  445.         return;
  446.  
  447.     for (pin = 0; pin < 4; pin++)
  448.         pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1));
  449.     for (pin = 0; pin < 4; pin++)
  450.         pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5));
  451. }
  452.  
  453. static struct pci_devemu pci_de_lpc = {
  454.     .pe_emu =   "lpc",
  455.     .pe_init =  pci_lpc_init,
  456.     .pe_write_dsdt = pci_lpc_write_dsdt,
  457.     .pe_cfgwrite =  pci_lpc_cfgwrite,
  458.     .pe_barwrite =  pci_lpc_write,
  459.     .pe_barread =   pci_lpc_read
  460. };
  461. PCI_EMUL_SET(pci_de_lpc);
  462.  
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