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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 10:02:34 02/08/2011
- // Design Name:
- // Module Name: project2
- // Project Name:
- // Target Devices:
- // Tool versions:
- // Description:
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module project2(
- input [3:0] buttons,
- input [1:0] switches,
- output [3:0] leds
- );
- reg [3:0] leds;
- always @ * begin
- case (switches)
- 0: leds = {buttons[1:0]}+{buttons[3:2]};
- 1: if (buttons==15)
- leds = 0;
- else begin
- leds[0]=buttons[0];
- leds[1]=buttons[0];
- leds[2]=buttons[1];
- leds[3]=buttons[2];
- end
- 2: if (buttons==0 || buttons==3 || buttons==6 || buttons==10 || buttons==13)
- leds=0;
- else if (buttons == 1 || buttons == 4 || buttons == 7 || buttons == 8 || buttons == 11 || buttons ==14)
- leds=1;
- else
- leds=2;
- 3: leds=~buttons;
- endcase
- end
- endmodule
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