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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date:    10:02:34 02/08/2011
  7. // Design Name:
  8. // Module Name:    project2
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module project2(
  22.     input [3:0] buttons,
  23.     input [1:0] switches,
  24.     output [3:0] leds
  25.     );
  26.      reg [3:0] leds;
  27.      always @ * begin
  28.      case (switches)
  29.      0: leds = {buttons[1:0]}+{buttons[3:2]};
  30.      1: if (buttons==15)
  31.          leds = 0;
  32.          else begin
  33.          leds[0]=buttons[0];
  34.          leds[1]=buttons[0];
  35.          leds[2]=buttons[1];
  36.          leds[3]=buttons[2];
  37.          end
  38.      2: if (buttons==0 || buttons==3 || buttons==6 || buttons==10 || buttons==13)
  39.             leds=0;
  40.          else if (buttons == 1 || buttons == 4 || buttons == 7 || buttons == 8 || buttons == 11 || buttons ==14)
  41.             leds=1;
  42.         else
  43.         leds=2;
  44.  
  45.  
  46.     3: leds=~buttons;
  47.     endcase
  48.     end
  49. endmodule
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