FF Enable Testbench

module reg_en_tst();
    reg D, clk, clr_, En;
    wire Q;
    reg_en uut (D,clk,clr_,En,Q);

    initial begin
     clk = 0;
     D = 0;
     En = 0;
     clr_ = 0;
    end
    always #10 D = D+1;
    initial #20 clr_ = 1;
    always #5 clk = ~clk;
    always #10 En = En+1;
    initial #100 $finish;
endmodule