-- Md. Sajid Altaf
-- 180041203

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_comparator IS
END tb_comparator;
ARCHITECTURE behavior OF tb_comparator IS
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT comparator
    PORT(
         clock : IN  std_logic;
         m : IN  std_logic_vector(7 downto 0);
         n : IN  std_logic_vector(7 downto 0);
         IAB : IN  std_logic;
         Output : OUT  std_logic
        );
    END COMPONENT;

   signal clock : std_logic := '0';
   signal m : std_logic_vector(7 downto 0) := (others => '0');
   signal n : std_logic_vector(7 downto 0) := (others => '0');
   signal IAB : std_logic := '0';

   signal Output : std_logic;

   constant clock_period : time := 10 ns;
 BEGIN

   uut: comparator PORT MAP (
          clock => clock,
          m => m,
          n => n,
          Imn => Imn,
          Output => Output
        );

   clock_process :process
   begin
 clock <= '0';
 wait for clock_period/2;
 clock <= '1';
 wait for clock_period/2;
   end process;

   stim_proc: process
   begin

      wait for 100 ns;
 m <= x"mm";
 n <= x"nn";
      wait for clock_period*10;
 n <= x"mm";

      wait;
   end process;

END;