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Sajid05

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Jan 7th, 2021
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  1. -- Md. Sajid Altaf
  2. -- 180041203
  3.  
  4. LIBRARY ieee;
  5. USE ieee.std_logic_1164.ALL;
  6.  
  7. ENTITY tb_comparator IS
  8. END tb_comparator;
  9. ARCHITECTURE behavior OF tb_comparator IS
  10.     -- Component Declaration for the Unit Under Test (UUT)
  11.     COMPONENT comparator
  12.     PORT(
  13.          clock : IN  std_logic;
  14.          m : IN  std_logic_vector(7 downto 0);
  15.          n : IN  std_logic_vector(7 downto 0);
  16.          IAB : IN  std_logic;
  17.          Output : OUT  std_logic
  18.         );
  19.     END COMPONENT;
  20.    
  21.    signal clock : std_logic := '0';
  22.    signal m : std_logic_vector(7 downto 0) := (others => '0');
  23.    signal n : std_logic_vector(7 downto 0) := (others => '0');
  24.    signal IAB : std_logic := '0';
  25.  
  26.    signal Output : std_logic;
  27.    
  28.    constant clock_period : time := 10 ns;
  29.  BEGIN
  30.  
  31.    uut: comparator PORT MAP (
  32.           clock => clock,
  33.           m => m,
  34.           n => n,
  35.           Imn => Imn,
  36.           Output => Output
  37.         );
  38.    
  39.    clock_process :process
  40.    begin
  41.  clock <= '0';
  42.  wait for clock_period/2;
  43.  clock <= '1';
  44.  wait for clock_period/2;
  45.    end process;
  46.    
  47.    stim_proc: process
  48.    begin
  49.      
  50.       wait for 100 ns;
  51.  m <= x"mm";
  52.  n <= x"nn";
  53.       wait for clock_period*10;
  54.  n <= x"mm";
  55.        
  56.       wait;
  57.    end process;
  58.  
  59. END;
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