1. Consider a magnetic disk drive with 8 surfaces, 512 tracks 64 sectors sector size 1kb average seek time 8ms 1.5 ms 3600rpm.

- Cylinder capacity = 8 * 64 * 1kb = 512kb

- Seek time = 8ms

- Rotational latency = 1/2 * 60/3600*2 = 8.3ms

- MB means that we need an IO cylinder, so 9 times track to track access time needed to access 10 cylinders. i.e transfer tme + 9 * track to track access tme 1 track transfer time = 80 * 60/ 3.6ms = 133.33ms

- Total time = seek time + 10 * (per track transfer time + rotational latency) + 9 * (track to track access time) => 8+ 10 * (133.33 + 8.3) + 9 * 1.5 = 1425.5ms

2. Advantages of RAID5 over RAID4

- RAID5 is organized in a similar fashion to RAID4.
The difference is that RAID5 distributes the parity strips across all disks. The distribution of parity strips across all drives avoids the potential I/O bottleneck found in RAID4

3. Compare direct mapping with accociative mapping.

- DIRECT MAPPING is the simplest technique, it maps each block of main memory into only one possible cache line.

- ASSOCIATIVE MAPPING overcomes the disadvantage of direct mapping by permitting each main memory block to be loaded into any line of the cache.

4. Explain the relation between cache size and hit rate

- AS THE BLOCK SIZE increases from very small to larger sizes, the hit ratio will at first increase because of the principle of locality, which states that data in the vicinity of a refferenced word are likely to be refferenced in the near future. As the block size increases, more useful useful data is brought into the cache and hit ratio will begin to decrease.
- The greater the cache size is, the less likely is for cache misses to occur. Since the formula for cache hit rate is cache hits/cache hits + misses, the bigger the cache size is, there is less misses. Therefore, the hit rate is higher in percentage

5. Dif between logical cache and physical.

- LOGICAL CACHE stores data using initial addresses. The processor accesses the cache directly without going through the MMU.

-PHYSICAL CACHE  stores data using main memory physical addresses. A physical cache is located between the MMU and main memory

- VIRTUAL CACHE access speed is greater than physical cache

6. Benefits of increasing bus width.

- THE WIDTH of the data bus is the key factor in determining overall system performance.

EXAMPLE: If the data bus is 32 bits wide and each instruction is 64 bits long then the processor must access the memory module twice during each instruction cycle.

7. Purpose of registers MAR, MBR, IR, PC

- MAR: Contains the address of a location in memory

- MBR: Contains a word of data to be written to memory or the word most recently read

- IR: Contains the instruction most recently fetched

- PC: Contains the address of an instruction to be fetched

FINAL

1. Briefly explain how the size of instructions affect design of computer systems

2. Briefly explain how the number of operands in the instructions affect the design of hardware

3. How to determine the width of program counter in terms of bits

4. Differences between segmentation and paging:

   -Page is always at fixed block size whereas a segment is at variable size
   -The size of the page is decided or specified by the hardware.The size of the segment is specified by the user.
   -In paging,the user only provides a single integer as the address which is divided by the hardware into a page number and offset.
     In segmentation the user specifies the address in two quantites i.e segment number and offset

5. Briefly explain how choosing addressing which addressing models will be used affects the design of computer hardware.

- ADDRESSING modes are an aspect of the instruction set architecture in most CPU designs.The various addressing modes that are defined in a given instruction set architecture
define how machine language instructions in that architecture identify the operand of each instruction.Addressing mode specifies how to calculate the effective memory address at
an operand by using information held in register and/or constants contained within a machine instruction or elsewhere.

6. Explain how I/O channels improve the performance of computer systems

-An important determinant of performance in many parallel programs is the time required to move data between memory and secondary storage,that is the time required for input/output


7. What are the 4 methods to deal with multiple interrupts? Explain them briefly

a)  PROVIDING MULTIPLE INTERRUPT LINES

First method for dealing with multiple interrupts is providing multiple interrupt lines between processor and I/O modules.This technique is impractical because it is very hard to dedicate more than few bus lines or processor pins to interrupt lines.Beacause of that,albeit we would use this technique,it is certain that each line will have multiple I/O modules attached to it and thus,it is needed to use one of other three techniques on each line

b)   SOFTWARE POLL

In this technique,when processor detects an interrupt,it branches to an interrupt-service routine that polls each I/O module to determine which module caused the interrupt.It can be done on two ways.First,the poll can be in form of TEST I/O.Then processor raises TEST I/O and puts the address of a particular I/O module on the address line and the I/O module responds positively if it set an interrupt.Second way is that module can contain addressable status register.Then processor read status register of each I/O module to identify module which caused the interrupt.When interrupting module is identified,processor branches to a device-service routine specific to that device.This technique has disadvantage because it is time consuming.

c)   DAISY CHAIN

Third technique is DAISY CHAIN and it provides a hardware poll. This technique is more efficient to use than SOFTWARE POLL. I/O modules use the same interrupt request line which is daisy chained through the modules.When processor senses that interrupt happened, it sends interrupt acknowledge by this line and that signal is propagating through the modules until it comes to the requesting module.Requesting module typically responds by putting word on data lines. That word is called vector and whole technique is also called VECTORED INTERRUPT. Vector is used as pointer to appropriate device-service routine and by this technique we avoid executing general interrupt-service routine.

d)   BUS ARBITRATION

BUS ARBITRATION is technique which also use vectored interrupt. In this technique I/O module first have to take control of the bus how it could raise the interrupt request line. On this way,only one module can raise the line at a time. When processor detects an interrupt,it responds on interrupt acknowledge line and requesting module then places its vector on the data lines.

8. Explain how demand paging mechanism works

Demand paging works on next way: Each page of process which should be performed will be brought only when there is need for it,by the other words,on demand. For better explanation of demand paging, I will use an example from our book. If we imagine a very big process which is consisted of long program plus a number of arrays of data. After any time,it may be needed to execute only small section of the program and it may be enough to use only several arrays of data. Then it would be wasting a time to load all pages when it is needed only few pages before program is suspended.



9. Briefly explain how using the pipeline mechanism increases the performance of computers.

-Pipelining increases performances of computer by increasing instruction throughput.Pipelining allows fetching next instructions while processor do arithmetic operations,holding them in buffer close to the processor until each instruction operation can be performed.