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-- Company:
-- Engineer:
--
-- Create Date: 10/23/2019 02:55:09 PM
-- Design Name:
-- Module Name: automat - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity automat_e is
 Port (I,clk:in STD_LOGIC;
     Q:out STD_LOGIC);
end automat_e;

architecture automat_a of automat_e is
Type myType is (S0,S1,S11,S110,S1101);
signal pr_state,nx_state: myType;
begin
process(clk,I,pr_state,nx_state)
begin
 case pr_state is
 when S0=>
    if (I='1' and rising_edge(clk)) then
    nx_state <= S1; Q<='0';
    elsif (I='0') then
    nx_state <= S0;
    end if;
    when S1=>
        if (I='1' and rising_edge(clk)) then
        nx_state <= S11; Q<='0';
        elsif (I='0') then
        nx_state <= S0;
        end if;
        when S11=>
            if (I='0' and rising_edge(clk)) then
            nx_state <= S110; Q<='0';
            elsif (I='1') then
            nx_state <= S0;
            end if;
when S110=>
                if (I='1' and rising_edge(clk)) then
                nx_state <= S1101; Q<='0';
                elsif (I='0') then
                nx_state <= S0;
                end if;
                when S1101=>
                    if (I='1' and rising_edge(clk)) then
                    Q <='1';
                    end if;
    end case;
end process;
end automat_a;