library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FSMexample is
    Port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC;
           INPUTA : in STD_LOGIC;
           INPUTB : in STD_LOGIC;
           OUTPUTA : out STD_LOGIC;
           OUTPUTB : out STD_LOGIC);
end FSMexample;

architecture Behavioral of FSMexample is

-- signal to store the FSM state in. Start at 0 state
signal state : std_logic_vector(1 downto 0) := "00";

begin

-- Logic to handle our outputs as a function of the current state.
-- Note that these are not tied to the clock directly but are instead
-- tied to the state variable that is synchronised to the clock for everything
-- except an asynchronous reset
OUTPUTA <= '1' when (state = "00" or state = "11") else '0';
OUTPUTB <= '1' when (state = "00" or state = "01") else '0';

-- process to handle our state transitions that is sensitive to the clock and a reset
process(CLK, RST)
    begin
        if RST = '1' then
            -- This is the reset case, set the state back to 0
            state <= "00";

        elsif rising_edge(CLK) then
            -- This is where our state transition logic fits we'll handle the transition out of
            -- each state with a case block

            case state is
                when "00" =>
                    -- State transition logic for state 00
                    if INPUTA = '0' AND INPUTB = '0' then
                        state <= "10";
                    end if;

                when "01" =>
                    -- State transition logic for state 01
                    if INPUTA = '1' AND INPUTB = '1' then
                        state <= "11";
                    end if;


                when "10" =>
                    -- State transition logic for state 10
                    if INPUTB = '1' then
                        state <= "01";
                    end if;

                when "11" =>
                    -- State transition logic for state 11
                    if INPUTA /= INPUTB then
                        state <= "00";
                    end if;

            end case;
        end if;
end process;

end Behavioral;