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itsme_rudj

Priority Encoder Testbench

Dec 8th, 2023
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VeriLog 0.53 KB | Source Code | 0 0
  1. module priority_tst();
  2.     reg [3:0] W;
  3.     wire [1:0] Y;
  4.     wire Z;
  5.     priority uut ( W, Y, Z);
  6.         initial begin
  7.             W = 4'b0001;
  8.         #10 W = 4'b0010;
  9.         #10 W = 4'b0011;
  10.         #10 W = 4'b0100;
  11.         #10 W = 4'b0101;
  12.         #10 W = 4'b0110;
  13.         #10 W = 4'b0111;
  14.         #10 W = 4'b1000;
  15.         #10 W = 4'b1001;
  16.         #10 W = 4'b1010;
  17.         #10 W = 4'b1011;
  18.         #10 W = 4'b1100;
  19.         #10 W = 4'b1101;
  20.         #10 W = 4'b1110;
  21.         #10 W = 4'b1111;
  22.         end
  23. endmodule
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