library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity dc_parity is
  port
  ( d   : in std_logic_vector (3 downto 0);
    q   : out std_logic_vector (3 downto 0);
    f   : out std_logic );
end dc_parity;




ARCHITECTURE behv OF dc_parity IS

signal m0, m1 , m2, m3, m4, m5, m6, m7: STD_LOGIC;

BEGIN

m0 <= not d(3) and not d(2) and not d(1);
m1 <= not d(3) and not d(2) and d(1);
m2 <= not d(3) and d(2) and not d(1);
m3 <= not d(3) and d(2) and d(1);
m4 <= d(3) and not d(2) and not d(1);
m5 <= d(3) and not d(2) and d(1);
m6 <= d(3) and d(2) and not d(1);
m7 <= d(3) and d(2) and d(1);

q(3) <= 0;
q(2) <= d(3);
q(1) <= d(2);
q(0) <= d(1);

f <= (1 xor d0) when (m0 or m3 or m5 or m6) else
   (d0);

END behv;