module try2 (
    input wire clk,
    output wire led1,
    output wire led2,
    output wire led3,
    output wire led4
);

    reg [27:0] counter;

    initial counter = 0;

    always @(posedge clk)
        counter <= counter + 1'b1;

    assign led1 = ~counter[27];
    assign led2 = ~counter[26];
    assign led3 = ~counter[25];
    assign led4 = ~counter[24];

endmodule