module sys(CLK, Qreg, SEG);

input CLK;
output [7:0] SEG;
output [3:0] Qreg; // krazace zero
wire [3:0] BIN;

reg0 myReg(CEO, Qreg);
CNT myCNT(CLK,1'b0,1'b1,,CEO);
MUX myMUX(CEO, 4'b0010, 4'b0000, 4'b0001, 4'b1000,Qreg,BIN);
SEG7 mySEG(BIN, SEG);

endmodule

module reg0(CLK,Q);
input CLK;
output [3:0] Q;
reg [3:0] Q;

always @(posedge CLK)
	case(Q)
		4'b0111 : Q <= 4'b1110;
		4'b1110 : Q <= 4'b1101;
		4'b1101 : Q <= 4'b1011;
		4'b1011 : Q <= 4'b0111;
		default : Q <= 4'b0111;
	endcase
endmodule

module CNT(CLK,CLR,CE,Q,CEO);
input CLK, CLR, CE;
output [18:0] Q;
reg [18:0] Q;
output CEO;

always @(posedge CLK or posedge CLR)
  if(CLR)
    Q <= 18'd0;
  else begin
    if(CE) begin
      if(Q != 18'd499_999)
			begin
			  Q <= Q + 1;
			 // CEO = 1'b0;
			end
      else
			begin
			  Q <= 18'd0;
			 // CEO = 1'b1;
			end
    end
  end
assign CEO = CE & (Q == 18'd499_999);
endmodule

module MUX(CLK, IN1, IN2, IN3, IN4, SEL, Q);

input CLK;
input [3:0] IN1, IN2, IN3, IN4;
input [3:0] SEL;
output [3:0] Q;
reg [3:0] Q;

always @(posedge CLK)
	case(SEL)
		4'b0111 : Q <= IN1;
		4'b1110 : Q <= IN2;
		4'b1101 : Q <= IN3;
		4'b1011 : Q <= IN4;
		default : Q <= IN1;
	endcase

endmodule


module SEG7(BIN, SEG);
input [3:0] BIN;
output [6:0] SEG;
reg [6:0] SEG;

   always @(BIN)
      case (BIN)
          4'b0001 : SEG = 7'b1111001;   // 1
          4'b0010 : SEG = 7'b0100100;   // 2
          4'b0011 : SEG = 7'b0110000;   // 3
          4'b0100 : SEG = 7'b0011001;   // 4
          4'b0101 : SEG = 7'b0010010;   // 5
          4'b0110 : SEG = 7'b0000010;   // 6
          4'b0111 : SEG = 7'b1111000;   // 7
          4'b1000 : SEG = 7'b0000000;   // 8
          4'b1001 : SEG = 7'b0010000;   // 9
          4'b1010 : SEG = 7'b0001000;   // A
          4'b1011 : SEG = 7'b0000011;   // b
          4'b1100 : SEG = 7'b1000110;   // C
          4'b1101 : SEG = 7'b0100001;   // d
          4'b1110 : SEG = 7'b0000110;   // E
          4'b1111 : SEG = 7'b0001110;   // F
          default : SEG = 7'b1000000;   // 0
      endcase
endmodule