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Sep 9th, 2018
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VHDL 2.40 KB | None | 0 0
  1.  
  2. LIBRARY IEEE;
  3. USE IEEE.Std_Logic_1164.ALL;
  4. use WORK.convpack.all;
  5. entity randomGen is
  6. generic (n:integer := 13; -- bit width
  7. pl:integer := 220);
  8. port (clock,reset: in STD_LOGIC;
  9. y: out STD_LOGIC_VECTOR(n-1 downto 0);
  10. pulse:out STD_LOGIC);
  11. end randomGen;
  12.  
  13.  
  14. architecture a01 of randomGen is
  15. type intArray is array (positive range <>) of integer;
  16.  
  17.  
  18. constant feedBackTable: intArray(1 to 5*15) :=
  19. -----------------------------------------------------------
  20. -- This table implements the taps, for the EXOR-feedback
  21. -- in the pseudo random generator.
  22. -- in the first column we have the number of feedbacks, for
  23. -- the bitWidth, indicated on the right side in the comment.
  24. -- the following numbers in a line are the feedback taps,
  25. -- we start counting positions from zero
  26.  
  27. -- taps | positions
  28. ( 2, 0, 1, 0, 0, -- for the minimum bitWith of 2
  29. 2, 2, 1, 0, 0, -- 3
  30. 2, 3, 2, 0, 0, -- 4
  31. 2, 4, 2, 0, 0, -- 5
  32. 2, 5, 4, 0, 0, -- 6
  33. 2, 6, 5, 0, 0, -- 7
  34. 4, 3, 4, 5, 7, -- 8
  35. 2, 8, 4, 0, 0, -- 9
  36. 2, 9, 6, 0, 0, -- 10
  37. 2, 10, 8, 0, 0, -- 11
  38. 0, 0, 0, 0, 0, -- no polynom for 12 bit found yet
  39. 0, 0, 0, 0, 0, -- neiter for 13 bit
  40. 0, 0, 0, 0, 0, -- neiter for 14 bit
  41. 2, 14,13, 0, 0, -- 15
  42. 4, 3, 12,14, 15);-- 16
  43.  
  44.  
  45. -- the following table is used to be able to synthesize the unit with 12,13
  46. -- and 14 bit, with an internal 15 bit register,
  47. -- the datawidth n will be replaced by internalN(n)
  48. constant internalN : intArray(2 to 32):=
  49. ( 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 15, 15, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16 );
  50.  
  51.  
  52.  
  53.  
  54.  
  55.  
  56. signal Q:STD_LOGIC_VECTOR(internalN(n)-1 downto 0);
  57.  
  58.  
  59. begin
  60.  
  61.  
  62. p01: process(reset,clock,Q)
  63. variable feedBack : STD_LOGIC;
  64. begin
  65. if (reset='1') then
  66. for i in (internalN(n)-1) downto 1 loop
  67. Q(i) <= '0';
  68. end loop;
  69. Q(0) <= '1';
  70. else
  71. if (clock'event) and (clock='1') then
  72. for i in 0 to internalN(n)-2 loop
  73. Q(i+1) <= Q(i);
  74. end loop;
  75. feedBack := Q(feedBackTable(5*internalN(n)+1-9));
  76. for i in 2 to feedBackTable(5*internalN(n)-9) loop
  77. feedBack := feedBack xor Q(feedBackTable(5*internalN(n)+i-9));
  78. end loop;
  79. Q(0) <= feedBack;
  80. end if;
  81. end if;
  82.  
  83. if n < 16 then
  84. y <= Q(internalN(n)-1 downto internalN(n)-n);-- (others => '0');
  85. else
  86. y <= (others => '0'); -- ugly random distribution
  87. y( internalN(n)-1 downto 0 ) <= Q( internalN(n)-1 downto 0 );
  88. end if;
  89.  
  90. if slv2int(Q) > pl then
  91. pulse <= '1';
  92. else
  93. pulse <= '0';
  94. end if;
  95. end process;
  96.  
  97.  
  98. end a01;
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