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- module fifo_arbiter(
- input A,
- input B,
- input C,
- input D,
- input CLK,
- output reg [3:0] fifo_take,
- output reg [1:0] ADDR,
- output reg READY
- );
- reg [3:0] states;
- initial begin
- states = 0;
- fifo_take <= 0;
- end
- always @(posedge CLK)
- begin
- if(A || B || C || D)
- begin
- if(A && ~ states[0] || states == {D, C, B, A} || fifo_take == {D, C, B, A})
- begin
- READY <= 1;
- ADDR <= 0;
- states[0] <= 1;
- fifo_take <= 1;
- end
- else
- begin
- if(B && ~states[1] || states == {D, C, B, A} || fifo_take == {D, C, B, A})
- begin
- READY <= 1;
- ADDR <= 1;
- states[1] <= 1;
- fifo_take <= 2;
- end
- else
- begin
- if(C && ~states[2] || states == {D, C, B, A} || fifo_take == {D, C, B, A})
- begin
- READY <= 1;
- ADDR <= 2;
- states[2] <= 1;
- fifo_take <= 4;
- end
- else
- begin
- if(D && ~states[3] || states == {D, C, B, A} || fifo_take == {D, C, B, A})
- begin
- READY <= 1;
- ADDR <= 3;
- states[3] <= 1;
- fifo_take <= 8;
- end
- else
- begin
- READY <= 0;
- states <= 0;
- fifo_take <= 0;
- end
- end
- end
- end
- end
- else
- begin
- READY <= 0;
- states <= 0;
- fifo_take <= 0;
- end
- end
- endmodule
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